From f8f0e3bbe1a485fa5671b11c006df410527d2f9f Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sat, 14 Jul 2018 18:53:32 -0400 Subject: Adjust Makefile to track source changes. --- build/Makefile | 2 -- 1 file changed, 2 deletions(-) (limited to 'build') diff --git a/build/Makefile b/build/Makefile index 4e3a9bb..d7c18f1 100644 --- a/build/Makefile +++ b/build/Makefile @@ -68,8 +68,6 @@ vfiles = \ $(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \ $(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \ ./core_selector.v \ - $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \ - $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \ -- cgit v1.2.3 From 297f59340bfcf4cfee141e9bedc2313fbac8b5ff Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:03:14 +0300 Subject: Corrected target device. --- build/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'build') diff --git a/build/Makefile b/build/Makefile index d7c18f1..f573ace 100644 --- a/build/Makefile +++ b/build/Makefile @@ -12,7 +12,7 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) project ?= alpha_fmc vendor = xilinx family = artix7 -part = xc7a200tfbg484-3 +part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -- cgit v1.2.3 From f13b5c416776498bdb7e8722016e14aaba442bfa Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:04:15 +0300 Subject: Use default synthesis options. --- build/xilinx.opt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'build') diff --git a/build/xilinx.opt b/build/xilinx.opt index 7fe9d8b..1ac8957 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -2,6 +2,7 @@ -ofmt NGC -opt_mode speed -opt_level 1 +-power NO -iuc NO -keep_hierarchy no -netlist_hierarchy as_optimized @@ -15,7 +16,7 @@ -case maintain -slice_utilization_ratio 100 -bram_utilization_ratio 100 -#-dsp_utilization_ratio 100 +-dsp_utilization_ratio 100 -safe_implementation No -fsm_extract YES -fsm_encoding Auto @@ -25,15 +26,19 @@ -rom_extract Yes -rom_style Auto -shreg_extract YES +-shreg_min_size 2 -auto_bram_packing NO -resource_sharing YES -async_to_sync NO -#-use_dsp48 auto +-use_dsp48 auto -iobuf YES --max_fanout 500 +-max_fanout 100000 +-bufg 32 -register_duplication YES -register_balancing No -optimize_primitives NO +-lc Auto +-reduce_control_sets Auto -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -- cgit v1.2.3 From 3abce31d6afdbbcb67b9dd5a160643a06d092861 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:08:54 +0300 Subject: 1. Disabled SmartGuide as it can thwart reproducible implementation. 2. Enabled multi-threading for MAP and PAR, the corresponding switch is -mt. MAP supports -mt off|2, PAR supports -mt off|2|3|4. Please revert back to -mt off if the build system has only two cores. --- build/xilinx.mk | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'build') diff --git a/build/xilinx.mk b/build/xilinx.mk index abeff7b..8c56319 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -33,8 +33,8 @@ coregen_work_dir ?= ./coregen-tmp #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: -map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -par_opts ?= -ol high +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off +par_opts ?= -ol high -mt 4 isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh flashsize ?= 8192 @@ -117,14 +117,17 @@ junk += $(project)_par.grf $(project)_par.ptwx junk += $(project)_par.unroutes $(project)_par.xpi $(project).ncd: $(project).ngd - if [ -r $(project)_par.ncd ]; then \ - cp $(project)_par.ncd smartguide.ncd; \ - smartguide="-smartguide smartguide.ncd"; \ - else \ - smartguide=""; \ - fi; \ + #if [ -r $(project)_par.ncd ]; then \ + # cp $(project)_par.ncd smartguide.ncd; \ + # smartguide="-smartguide smartguide.ncd"; \ + #else \ + # smartguide=""; \ + #fi; \ + #$(xil_env); \ + #map $(intstyle) $(map_opts) $$smartguide $< $(xil_env); \ - map $(intstyle) $(map_opts) $$smartguide $< + map $(intstyle) $(map_opts) $< + junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map junk += smartguide.ncd $(project).psr junk += $(project)_summary.xml $(project)_usage.xml -- cgit v1.2.3 From d507f5d8174bc7ba1fce82830c61195c16f14776 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Tue, 21 Aug 2018 15:06:04 -0400 Subject: Add explicit check for timing failure, per Pavel. --- build/xilinx.mk | 1 + 1 file changed, 1 insertion(+) (limited to 'build') diff --git a/build/xilinx.mk b/build/xilinx.mk index 8c56319..b2b67ce 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -111,6 +111,7 @@ $(project)_par.ncd: $(project).ncd else \ $(MAKE) etwr; \ fi + @ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad junk += $(project)_par_pad.csv $(project)_par_pad.txt junk += $(project)_par.grf $(project)_par.ptwx -- cgit v1.2.3 From 3de07e1508c4c8f2e4fe38994cf41eabee391119 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:10:19 -0400 Subject: Remove `-global_opt off` per discussion with Joachim and Pavel. --- build/xilinx.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'build') diff --git a/build/xilinx.mk b/build/xilinx.mk index b2b67ce..b8ea85c 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -33,7 +33,7 @@ coregen_work_dir ?= ./coregen-tmp #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: -map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt 2 -ir off -pr off -lc off -power off par_opts ?= -ol high -mt 4 isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh -- cgit v1.2.3 From 41e330bcd2eec0c9a871e82698959c742a3e8d09 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:15:43 -0400 Subject: Comment smartguide out of Makefile, not just out of shell script. --- build/xilinx.mk | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'build') diff --git a/build/xilinx.mk b/build/xilinx.mk index b8ea85c..e3ce440 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -118,14 +118,14 @@ junk += $(project)_par.grf $(project)_par.ptwx junk += $(project)_par.unroutes $(project)_par.xpi $(project).ncd: $(project).ngd - #if [ -r $(project)_par.ncd ]; then \ - # cp $(project)_par.ncd smartguide.ncd; \ - # smartguide="-smartguide smartguide.ncd"; \ - #else \ - # smartguide=""; \ - #fi; \ - #$(xil_env); \ - #map $(intstyle) $(map_opts) $$smartguide $< +# if [ -r $(project)_par.ncd ]; then \ +# cp $(project)_par.ncd smartguide.ncd; \ +# smartguide="-smartguide smartguide.ncd"; \ +# else \ +# smartguide=""; \ +# fi; \ +# $(xil_env); \ +# map $(intstyle) $(map_opts) $$smartguide $< $(xil_env); \ map $(intstyle) $(map_opts) $< -- cgit v1.2.3 From f8f86f9cfbd0ac73d2b0d3600e424b9c669cea59 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:24:39 -0400 Subject: Generate detailed timing report when PAR fails. The original version of this file appears to have been attempting to do this, but got the grotty details wrong. --- build/xilinx.mk | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'build') diff --git a/build/xilinx.mk b/build/xilinx.mk index e3ce440..9af9366 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -106,12 +106,10 @@ junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm $(project)_par.ncd: $(project).ncd $(xil_env); \ - if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \ - :; \ - else \ + if ! par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd || grep >/dev/null 'WARNING:Par:468' $(project)_par.par; then \ $(MAKE) etwr; \ + exit 1; \ fi - @ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad junk += $(project)_par_pad.csv $(project)_par_pad.txt junk += $(project)_par.grf $(project)_par.ptwx -- cgit v1.2.3 From f01086416f290352c2c9faa0f1c6b1fce31e8f01 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Mon, 14 Jan 2019 17:39:47 -0500 Subject: Add include directives for Pavel's .vh files. --- build/xilinx.opt | 1 + 1 file changed, 1 insertion(+) (limited to 'build') diff --git a/build/xilinx.opt b/build/xilinx.opt index 1ac8957..933f7df 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -45,3 +45,4 @@ -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 +-vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode} -- cgit v1.2.3 From 516b2975958b05c72f573c37c075e5793c514101 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 22 Jan 2019 19:39:09 -0500 Subject: Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0 (which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile. --- build/Makefile | 4 ++++ build/xilinx.mk | 1 + build/xilinx.opt | 1 - 3 files changed, 5 insertions(+), 1 deletion(-) (limited to 'build') diff --git a/build/Makefile b/build/Makefile index f573ace..60e55f9 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. diff --git a/build/xilinx.mk b/build/xilinx.mk index 9af9366..4bfefde 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -154,6 +154,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ + echo "-vlgincdir {$(vlgincdir)}" >> $@ cat ./xilinx.opt $(optfile) >> $@ junk += $(project).scr diff --git a/build/xilinx.opt b/build/xilinx.opt index 933f7df..1ac8957 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -45,4 +45,3 @@ -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 --vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode} -- cgit v1.2.3