From a69ef3c13244c5269a1ad1a48fdc736493005975 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 22 Jan 2019 19:39:09 -0500 Subject: Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0 (which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile. --- build/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'build/Makefile') diff --git a/build/Makefile b/build/Makefile index 5a6107d..60e55f9 100644 --- a/build/Makefile +++ b/build/Makefile @@ -16,11 +16,11 @@ part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf ?= ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf -# verilog include directories {yes, XST wants them exactly this way in curly braces} -vlgincdir = {$(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode} +# Verilog include directories, if needed +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode all: $(project).bit -- cgit v1.2.3