From a4e91b6221f75045dd1d97362e9d12c590ebc15a Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Thu, 21 Sep 2017 09:20:21 -0400
Subject: Separate FMC test from mainline top-level module.

---
 build/Makefile | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'build/Makefile')

diff --git a/build/Makefile b/build/Makefile
index 763ad5e..4e3a9bb 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -25,10 +25,10 @@ all:	$(project).bit
 CONFIG          = $(CORE_TREE)/platform/common/config
 CONFIG_BOARD	= alpha
 CONFIG_PROJECT	= hsm
-CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD) -p $(CONFIG_PROJECT)
+CONFIG_GEN      = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD)
 
 core_selector.v core_vfiles.mk:
-	$(CONFIG_GEN)
+	$(CONFIG_GEN) -p $(CONFIG_PROJECT)
 
 # Build some different configurations
 
@@ -56,6 +56,10 @@ hsm:
 	$(CONFIG_GEN) -p hsm
 	$(MAKE) project=$(project)_hsm ucf=$(ucf)
 
+hsm-super:
+	$(CONFIG_GEN) -p hsm-super
+	$(MAKE) project=$(project)_hsm-super ucf=$(ucf)
+
 # Verilog files that always go with builds on this platform.
 
 vfiles = \
-- 
cgit v1.2.3