From f8f0e3bbe1a485fa5671b11c006df410527d2f9f Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Sat, 14 Jul 2018 18:53:32 -0400 Subject: Adjust Makefile to track source changes. --- build/Makefile | 2 -- 1 file changed, 2 deletions(-) (limited to 'build/Makefile') diff --git a/build/Makefile b/build/Makefile index 4e3a9bb..d7c18f1 100644 --- a/build/Makefile +++ b/build/Makefile @@ -68,8 +68,6 @@ vfiles = \ $(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \ $(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \ ./core_selector.v \ - $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \ - $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \ $(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \ -- cgit v1.2.3 From 297f59340bfcf4cfee141e9bedc2313fbac8b5ff Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:03:14 +0300 Subject: Corrected target device. --- build/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'build/Makefile') diff --git a/build/Makefile b/build/Makefile index d7c18f1..f573ace 100644 --- a/build/Makefile +++ b/build/Makefile @@ -12,7 +12,7 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) project ?= alpha_fmc vendor = xilinx family = artix7 -part = xc7a200tfbg484-3 +part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -- cgit v1.2.3 From 516b2975958b05c72f573c37c075e5793c514101 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 22 Jan 2019 19:39:09 -0500 Subject: Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0 (which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile. --- build/Makefile | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'build/Makefile') diff --git a/build/Makefile b/build/Makefile index f573ace..60e55f9 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. -- cgit v1.2.3