From 7be8f9437441b07793e3b0f2a220cb15cc206354 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Mon, 27 Aug 2018 16:59:34 -0400 Subject: correct fpga part number, add keywrap build target --- build/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/build/Makefile b/build/Makefile index 4e3a9bb..8115637 100644 --- a/build/Makefile +++ b/build/Makefile @@ -12,7 +12,7 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) project ?= alpha_fmc vendor = xilinx family = artix7 -part = xc7a200tfbg484-3 +part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh @@ -60,6 +60,10 @@ hsm-super: $(CONFIG_GEN) -p hsm-super $(MAKE) project=$(project)_hsm-super ucf=$(ucf) +keywrap: + $(CONFIG_GEN) -p keywrap + $(MAKE) project=$(project)_keywrap ucf=$(ucf) + # Verilog files that always go with builds on this platform. vfiles = \ -- cgit v1.2.3 From af8de11dc0b5e138ae78be9d6b7bfa5724be3141 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 4 Dec 2018 15:12:43 -0500 Subject: Collapse build targets into one rule, because that's exactly what $@ is designed for. --- build/Makefile | 34 +++------------------------------- 1 file changed, 3 insertions(+), 31 deletions(-) diff --git a/build/Makefile b/build/Makefile index 8115637..4328fbd 100644 --- a/build/Makefile +++ b/build/Makefile @@ -32,37 +32,9 @@ core_selector.v core_vfiles.mk: # Build some different configurations -bare: - $(CONFIG_GEN) -p bare - $(MAKE) project=$(project)_bare ucf=$(ucf) - -trng: - $(CONFIG_GEN) -p trng - $(MAKE) project=$(project)_trng ucf=$(ucf) - -hash: - $(CONFIG_GEN) -p hash - $(MAKE) project=$(project)_hash ucf=$(ucf) - -rsa: - $(CONFIG_GEN) -p rsa - $(MAKE) project=$(project)_rsa ucf=$(ucf) - -mkmif: - $(CONFIG_GEN) -p mkmif - $(MAKE) project=$(project)_mkmif ucf=$(ucf) - -hsm: - $(CONFIG_GEN) -p hsm - $(MAKE) project=$(project)_hsm ucf=$(ucf) - -hsm-super: - $(CONFIG_GEN) -p hsm-super - $(MAKE) project=$(project)_hsm-super ucf=$(ucf) - -keywrap: - $(CONFIG_GEN) -p keywrap - $(MAKE) project=$(project)_keywrap ucf=$(ucf) +bare trng hash mkmif rsa hsm hsm-super keywrap: + $(CONFIG_GEN) -p $@ + $(MAKE) project=$(project)_$@ ucf=$(ucf) # Verilog files that always go with builds on this platform. -- cgit v1.2.3 From 36e8f3dc6cb62ecc53f36dfd798bf8196c4c758b Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 22 Jan 2019 19:39:09 -0500 Subject: Cherry-pick 8cd28d0/fe3d53c: Added `include directories to Makefile. --- build/Makefile | 4 ++++ build/xilinx.mk | 1 + 2 files changed, 5 insertions(+) diff --git a/build/Makefile b/build/Makefile index 4328fbd..6634de7 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. diff --git a/build/xilinx.mk b/build/xilinx.mk index abeff7b..76d0110 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -152,6 +152,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ + echo "-vlgincdir {$(vlgincdir)}" >> $@ cat ./xilinx.opt $(optfile) >> $@ junk += $(project).scr -- cgit v1.2.3 From 0415949a1e64f7e28cd2d319cb317c4da2b41b67 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:04:15 +0300 Subject: Use default synthesis options. --- build/xilinx.opt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/build/xilinx.opt b/build/xilinx.opt index 7fe9d8b..1ac8957 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -2,6 +2,7 @@ -ofmt NGC -opt_mode speed -opt_level 1 +-power NO -iuc NO -keep_hierarchy no -netlist_hierarchy as_optimized @@ -15,7 +16,7 @@ -case maintain -slice_utilization_ratio 100 -bram_utilization_ratio 100 -#-dsp_utilization_ratio 100 +-dsp_utilization_ratio 100 -safe_implementation No -fsm_extract YES -fsm_encoding Auto @@ -25,15 +26,19 @@ -rom_extract Yes -rom_style Auto -shreg_extract YES +-shreg_min_size 2 -auto_bram_packing NO -resource_sharing YES -async_to_sync NO -#-use_dsp48 auto +-use_dsp48 auto -iobuf YES --max_fanout 500 +-max_fanout 100000 +-bufg 32 -register_duplication YES -register_balancing No -optimize_primitives NO +-lc Auto +-reduce_control_sets Auto -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -- cgit v1.2.3 From 995f7178156c6f16484bbb7b8eed86ef86d222a8 Mon Sep 17 00:00:00 2001 From: "Pavel V. Shatov (Meister)" Date: Sat, 18 Aug 2018 02:08:54 +0300 Subject: 1. Disabled SmartGuide as it can thwart reproducible implementation. 2. Enabled multi-threading for MAP and PAR, the corresponding switch is -mt. MAP supports -mt off|2, PAR supports -mt off|2|3|4. Please revert back to -mt off if the build system has only two cores. --- build/xilinx.mk | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/build/xilinx.mk b/build/xilinx.mk index 76d0110..0250915 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -33,8 +33,8 @@ coregen_work_dir ?= ./coregen-tmp #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: -map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -par_opts ?= -ol high +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off +par_opts ?= -ol high -mt 4 isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh flashsize ?= 8192 @@ -117,14 +117,17 @@ junk += $(project)_par.grf $(project)_par.ptwx junk += $(project)_par.unroutes $(project)_par.xpi $(project).ncd: $(project).ngd - if [ -r $(project)_par.ncd ]; then \ - cp $(project)_par.ncd smartguide.ncd; \ - smartguide="-smartguide smartguide.ncd"; \ - else \ - smartguide=""; \ - fi; \ + #if [ -r $(project)_par.ncd ]; then \ + # cp $(project)_par.ncd smartguide.ncd; \ + # smartguide="-smartguide smartguide.ncd"; \ + #else \ + # smartguide=""; \ + #fi; \ + #$(xil_env); \ + #map $(intstyle) $(map_opts) $$smartguide $< $(xil_env); \ - map $(intstyle) $(map_opts) $$smartguide $< + map $(intstyle) $(map_opts) $< + junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map junk += smartguide.ncd $(project).psr junk += $(project)_summary.xml $(project)_usage.xml -- cgit v1.2.3 From 56c22fbc58466285af8ac8f7ea7f48fc78212311 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Tue, 21 Aug 2018 15:06:04 -0400 Subject: Add explicit check for timing failure, per Pavel. --- build/xilinx.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/build/xilinx.mk b/build/xilinx.mk index 0250915..e1cc9bc 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -111,6 +111,7 @@ $(project)_par.ncd: $(project).ncd else \ $(MAKE) etwr; \ fi + @ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad junk += $(project)_par_pad.csv $(project)_par_pad.txt junk += $(project)_par.grf $(project)_par.ptwx -- cgit v1.2.3 From bb2d178c63e99abf78a30281625bc9826f19fff6 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:10:19 -0400 Subject: Remove `-global_opt off` per discussion with Joachim and Pavel. --- build/xilinx.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build/xilinx.mk b/build/xilinx.mk index e1cc9bc..35c8616 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -33,7 +33,7 @@ coregen_work_dir ?= ./coregen-tmp #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk: -map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off +map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt 2 -ir off -pr off -lc off -power off par_opts ?= -ol high -mt 4 isedir ?= /opt/Xilinx/13.3/ISE_DS xil_env ?= . $(isedir)/settings32.sh -- cgit v1.2.3 From 3d9123b5f2a496e3c3c7469f33eeec98c910004e Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:15:43 -0400 Subject: Comment smartguide out of Makefile, not just out of shell script. --- build/xilinx.mk | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/build/xilinx.mk b/build/xilinx.mk index 35c8616..99f86ef 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -118,14 +118,14 @@ junk += $(project)_par.grf $(project)_par.ptwx junk += $(project)_par.unroutes $(project)_par.xpi $(project).ncd: $(project).ngd - #if [ -r $(project)_par.ncd ]; then \ - # cp $(project)_par.ncd smartguide.ncd; \ - # smartguide="-smartguide smartguide.ncd"; \ - #else \ - # smartguide=""; \ - #fi; \ - #$(xil_env); \ - #map $(intstyle) $(map_opts) $$smartguide $< +# if [ -r $(project)_par.ncd ]; then \ +# cp $(project)_par.ncd smartguide.ncd; \ +# smartguide="-smartguide smartguide.ncd"; \ +# else \ +# smartguide=""; \ +# fi; \ +# $(xil_env); \ +# map $(intstyle) $(map_opts) $$smartguide $< $(xil_env); \ map $(intstyle) $(map_opts) $< -- cgit v1.2.3 From bf5f9958e677ffce2e65b683f8101273c1fcb468 Mon Sep 17 00:00:00 2001 From: Rob Austein Date: Mon, 27 Aug 2018 11:24:39 -0400 Subject: Generate detailed timing report when PAR fails. The original version of this file appears to have been attempting to do this, but got the grotty details wrong. --- build/xilinx.mk | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/build/xilinx.mk b/build/xilinx.mk index 99f86ef..4bfefde 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -106,12 +106,10 @@ junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm $(project)_par.ncd: $(project).ncd $(xil_env); \ - if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \ - :; \ - else \ + if ! par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd || grep >/dev/null 'WARNING:Par:468' $(project)_par.par; then \ $(MAKE) etwr; \ + exit 1; \ fi - @ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad junk += $(project)_par_pad.csv $(project)_par_pad.txt junk += $(project)_par.grf $(project)_par.ptwx -- cgit v1.2.3 From 97aaac4da6e33e218b26c1963ab563e9e2c11e82 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Mon, 27 Aug 2018 16:59:34 -0400 Subject: correct fpga part number, add keywrap build target --- build/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/build/Makefile b/build/Makefile index ca5d735..22fd1f4 100644 --- a/build/Makefile +++ b/build/Makefile @@ -40,6 +40,10 @@ bare trng hash mkmif rsa hsm hsm-super: $(CONFIG_GEN) -p $@ $(MAKE) project=$(project)_$@ ucf=$(ucf) +keywrap: + $(CONFIG_GEN) -p keywrap + $(MAKE) project=$(project)_keywrap ucf=$(ucf) + # Verilog files that always go with builds on this platform. vfiles = \ -- cgit v1.2.3 From 73f5aa59d7bd4ff3b1b794c94b734727572c5986 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 4 Dec 2018 15:12:43 -0500 Subject: Collapse build targets into one rule, because that's exactly what $@ is designed for. --- build/Makefile | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/build/Makefile b/build/Makefile index 22fd1f4..2fc9fe0 100644 --- a/build/Makefile +++ b/build/Makefile @@ -36,14 +36,10 @@ core_selector.v core_vfiles.mk: # Build some different configurations -bare trng hash mkmif rsa hsm hsm-super: +bare trng hash mkmif rsa hsm hsm-super keywrap: $(CONFIG_GEN) -p $@ $(MAKE) project=$(project)_$@ ucf=$(ucf) -keywrap: - $(CONFIG_GEN) -p keywrap - $(MAKE) project=$(project)_keywrap ucf=$(ucf) - # Verilog files that always go with builds on this platform. vfiles = \ -- cgit v1.2.3