From 7287778d11c63b9c97f7aa01993bb17a76b058a6 Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Tue, 18 Feb 2020 19:50:06 -0500 Subject: add support for modexpng --- build/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/build/Makefile b/build/Makefile index ca5d735..92414de 100644 --- a/build/Makefile +++ b/build/Makefile @@ -20,7 +20,8 @@ ucf ?= ../ucf/$(project).ucf # Verilog include directories, if needed -vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode +MODEXPNG = ../../../../user/shatov/modexpng/rtl +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode $(MODEXPNG) $(CORE_TREE)/lib/util all: $(project).bit @@ -36,7 +37,7 @@ core_selector.v core_vfiles.mk: # Build some different configurations -bare trng hash mkmif rsa hsm hsm-super: +bare trng hash mkmif rsa hsm hsm-super modexpng hsm-modexpng: $(CONFIG_GEN) -p $@ $(MAKE) project=$(project)_$@ ucf=$(ucf) -- cgit v1.2.3