From 501064346da2ce981b4a02992dabb9c2eff76b38 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Thu, 5 Jul 2018 21:37:27 +0300
Subject: Updated constraints.

---
 ucf/alpha_fmc.ucf | 49 +++++++++++++++----------------------------------
 1 file changed, 15 insertions(+), 34 deletions(-)

diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index 5e71c64..efefa76 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -7,7 +7,7 @@
 #
 #
 # Author: Pavel Shatov
-# Copyright (c) 2016, NORDUnet A/S All rights reserved.
+# Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
@@ -39,23 +39,23 @@
 
 
 #--------------------------------------------------------------------------------
-# GCLK Timing (fixed at 50 MHz)
+# GCLK Timing (fixed at 50 MHz) - NOT USED
 #--------------------------------------------------------------------------------
-NET  "gclk_pin" TNM_NET = TNM_gclk;
-TIMESPEC  TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
+#NET  "gclk_pin" TNM_NET = TNM_gclk;
+#TIMESPEC  TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
 
 
 #-------------------------------------------------------------------------------
 # FMC_CLK Timing (can be up to 90 MHz)
 #-------------------------------------------------------------------------------
 NET  "fmc_clk" TNM_NET = TNM_fmc_clk;
-TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
+TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%;
 
 
 #-------------------------------------------------------------------------------
 # FPGA Pinout
 #-------------------------------------------------------------------------------
-#
+#
 NET "led_pins<0>" LOC = "U3";
 NET "led_pins<1>" LOC = "T1";
 NET "led_pins<2>" LOC = "W22";
@@ -145,8 +145,9 @@ NET  "mkm_do"          LOC = "Y1"   | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
 # FMC Input Timing
 #-------------------------------------------------------------------------------
 #
-# The following timing values were derived from pages 173-175 of the STM32F429
-# datasheet. Control signals NE1, NL and NWE all have different timing values.
+# The following timing values were derived from Figures 61-62 and Tables 96-97
+# (pages 180-182) of the STM32F429 datasheet ("DocID024030 Rev 10").
+# Control signals NE1, NL and NWE all have different timing values.
 # Instead of writing individual constraints for every control signal, the most
 # strict constraint is applied to all control signals. This should not cause
 # any P&R issues, since Spartan-6 (and Artix-7) can handle 90 MHz easily.
@@ -154,10 +155,9 @@ NET  "mkm_do"          LOC = "Y1"   | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
 # NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
 #
 # Data and Address buses also have different timings, with Data bus timing being
-# more strict. The same approach is used here, i.e. timing for Data bus is
-# applied to Address bus too.
+# more strict.
 #
-# Oh, and stupid datasheet doesn't explicitly specify hold time for the data bus!
+# Oh, and the datasheet doesn't explicitly specify hold time for the data bus.
 #
 
 NET  "fmc_d<*>" TNM = "TNM_FMC_IN_DATA" ;
@@ -167,37 +167,18 @@ NET  "fmc_ne1"  TNM = "TNM_FMC_IN_CONTROL" ;
 NET  "fmc_nl"   TNM = "TNM_FMC_IN_CONTROL" ;
 NET  "fmc_nwe"  TNM = "TNM_FMC_IN_CONTROL" ;
 
-TIMEGRP  "TNM_FMC_IN_DATA"    OFFSET = IN 3.0 ns VALID  6.0 ns BEFORE "fmc_clk" RISING ;
-TIMEGRP  "TNM_FMC_IN_ADDR"    OFFSET = IN 3.0 ns VALID  6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP  "TNM_FMC_IN_DATA"    OFFSET = IN 3.0 ns VALID  8.5 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP  "TNM_FMC_IN_ADDR"    OFFSET = IN 5.5 ns VALID  5.5 ns BEFORE "fmc_clk" RISING ;
 TIMEGRP  "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk" RISING ;
 
+
 #-------------------------------------------------------------------------------
 # FMC Output Timing
 #-------------------------------------------------------------------------------
-#
-# NWAIT signal is not constrained, since it is polled by STM32.
-#
-
 NET  "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
 
-TIMEGRP  "TNM_FMC_OUT_DATA" OFFSET = OUT 16.7 ns AFTER "fmc_clk" FALLING;
-
+TIMEGRP  "TNM_FMC_OUT_DATA" OFFSET = OUT 6.0 ns AFTER "fmc_clk" RISING;
 
-#-------------------------------------------------------------------------------
-# CDC Paths
-#-------------------------------------------------------------------------------
-INST  "fmc/fmc_cdc/cdc_fmc_sys/src_ff"     TNM = "TNM_from_fmc_clk";
-INST  "fmc/fmc_cdc/cdc_fmc_sys/src_latch*" TNM = "TNM_from_fmc_clk";
-INST  "fmc/fmc_cdc/cdc_fmc_sys/ff_sync*"   TNM = "TNM_to_sys_clk";
-INST  "fmc/fmc_cdc/cdc_fmc_sys/dst_latch*" TNM = "TNM_to_sys_clk";
-
-INST  "fmc/fmc_cdc/cdc_sys_fmc/src_ff"     TNM = "TNM_from_sys_clk";
-INST  "fmc/fmc_cdc/cdc_sys_fmc/src_latch*" TNM = "TNM_from_sys_clk";
-INST  "fmc/fmc_cdc/cdc_sys_fmc/ff_sync*"   TNM = "TNM_to_fmc_clk";
-INST  "fmc/fmc_cdc/cdc_sys_fmc/dst_latch*" TNM = "TNM_to_fmc_clk";
-
-TIMESPEC  "TS_fmc_clk_2_sys_clk" = FROM "TNM_from_fmc_clk" TO "TNM_to_sys_clk" TIG;
-TIMESPEC  "TS_sys_clk_2_fmc_clk" = FROM "TNM_from_sys_clk" TO "TNM_to_fmc_clk" TIG;
 
 #======================================================================
 # EOF alpha_fmc.ucf
-- 
cgit v1.2.3


From a92607244570328d815fa90d032620766fd21193 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Thu, 5 Jul 2018 21:39:08 +0300
Subject: Added phase shift to MMCM.

---
 rtl/clkmgr_mmcm.v | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/rtl/clkmgr_mmcm.v b/rtl/clkmgr_mmcm.v
index 852288b..03b0747 100644
--- a/rtl/clkmgr_mmcm.v
+++ b/rtl/clkmgr_mmcm.v
@@ -6,7 +6,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -38,22 +38,23 @@
 
 module clkmgr_mmcm
   (
-   input wire  clk_in,
+   input wire  gclk_in,
    input wire  reset_in,
   
    output wire gclk_out,
    output wire gclk_missing_out,
 
-   output wire clk_out,
+   output wire clk_out,
    output wire clk_valid_out
    );
    
    
-   //
-   // Parameters
-   //
-   parameter    CLK_OUT_MUL     = 20.0;    // multiply factor for output clock frequency (2..64)
-   parameter    CLK_OUT_DIV     = 20.0;    // divide factor for output clock frequency (1..128)
+    //
+    // Parameters
+    //
+    parameter    CLK_OUT_MUL     = 12.0;    // multiply factor for output clock frequency (2..64)
+    parameter    CLK_OUT_DIV     = 12.0;    // divide factor for output clock frequency (1..128)
+    parameter	 CLK_OUT_PHI	 = 45.0;    // clock phase shift (0.0..360.0)
    
    
    //
@@ -61,12 +62,12 @@ module clkmgr_mmcm
    //
  
    (* BUFFER_TYPE="NONE" *)
-	wire        clk_in_ibufg;
+	wire        gclk_in_ibufg;
 	
 	IBUFG IBUFG_gclk
    (
-		.I (clk_in),
-		.O	(clk_in_ibufg)
+		.I (gclk_in),
+		.O	(gclk_in_ibufg)
 	);
 
 
@@ -80,7 +81,7 @@ module clkmgr_mmcm
 	
 	MMCME2_ADV #
 	(
-		.CLKIN1_PERIOD        (20.000),
+		.CLKIN1_PERIOD        (11.111),
 		.REF_JITTER1          (0.010),
 
 		.STARTUP_WAIT         ("FALSE"),
@@ -94,7 +95,7 @@ module clkmgr_mmcm
 		.CLKFBOUT_USE_FINE_PS ("FALSE"),
 		
 		.CLKOUT0_DIVIDE_F     (CLK_OUT_DIV),
-		.CLKOUT0_PHASE        (0.000),
+		.CLKOUT0_PHASE        (CLK_OUT_PHI),
 		.CLKOUT0_USE_FINE_PS  ("FALSE"),
 		.CLKOUT0_DUTY_CYCLE   (0.500),
 		
@@ -102,7 +103,7 @@ module clkmgr_mmcm
 	)
 	MMCME2_ADV_inst
 	(
-		.CLKIN1              (clk_in_ibufg),
+		.CLKIN1              (gclk_in_ibufg),
 		.CLKIN2              (1'b0),
 		.CLKINSEL            (1'b1),
 
@@ -151,7 +152,7 @@ module clkmgr_mmcm
 	//
 	// Mapping
 	//
-	assign	gclk_out        = clk_in_ibufg;
+	assign	gclk_out        = gclk_in_ibufg;
 	assign	clk_valid_out   = mmcm_locked;
 
 	
-- 
cgit v1.2.3


From fea771cc459e2aeec1177ad30464f591fc3a0bc5 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Thu, 5 Jul 2018 21:39:55 +0300
Subject: Updated clock manager.

---
 rtl/alpha_clkmgr.v | 38 ++++++++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v
index f870a75..5c4099e 100644
--- a/rtl/alpha_clkmgr.v
+++ b/rtl/alpha_clkmgr.v
@@ -7,7 +7,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -39,19 +39,28 @@
 
 module alpha_clkmgr
   (
-   input wire  gclk,            // signal from clock pin
+   input wire  fmc_clk,         // signal from clock pin
 
-   output wire sys_clk,         // buffered system clock output
+   output wire sys_clk,         // buffered system clock output
    output wire sys_rst_n        // system reset output (async set, sync clear, active-low)
    );
 
 
    //
-   // Parameters
-   //
-   parameter    CLK_OUT_MUL     = 20.0;
-   parameter    CLK_OUT_DIV     = 20.0;
-
+   // Settings
+   //
+	
+	/*
+	 * fmc_clk is 90 MHz, sys_clk is also 90 MHz routed through an MMCM.
+	 *
+	 * VCO frequency is 1080 MHz.
+	 *
+	 */
+   localparam CLK_OUT_MUL   = 12.0;
+   localparam CLK_OUT_DIV   = 12.0;
+   localparam CLK_OUT_PHI   = 45.0;
+
+
    //
    // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
    //
@@ -63,21 +72,22 @@ module alpha_clkmgr
 
    clkmgr_mmcm #
      (
-			.CLK_OUT_MUL              (CLK_OUT_MUL),	// 2..64
-			.CLK_OUT_DIV              (CLK_OUT_DIV)	// 1..128
+			.CLK_OUT_MUL (CLK_OUT_MUL),	// 2..64
+			.CLK_OUT_DIV (CLK_OUT_DIV),	// 1..128
+			.CLK_OUT_PHI (CLK_OUT_PHI)	// 0.0..360.0
       )
    mmcm
      (
-      .clk_in                   (gclk),
+      .gclk_in                  (fmc_clk),
       .reset_in                 (mmcm_reset),
 
       .gclk_out                 (gclk_int),
       .gclk_missing_out         (gclk_missing),
 
-      .clk_out                  (sys_clk),
+      .clk_out                  (sys_clk),
       .clk_valid_out            (mmcm_locked)
       );
-		
+      		
 
 
    //
@@ -93,7 +103,7 @@ module alpha_clkmgr
 
    always @(posedge gclk_int or posedge gclk_missing)
      //
-     if ((gclk_missing == 1'b1))
+     if (gclk_missing == 1'b1)
        mmcm_rst_shreg    <= {16{1'b1}};
      else
        mmcm_rst_shreg    <= {mmcm_rst_shreg[14:0], 1'b0};
-- 
cgit v1.2.3


From ff1faf971a87362f9e0664dcfcf6bb447b043aeb Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Thu, 5 Jul 2018 21:40:51 +0300
Subject: Changed top module to accomodate changes to the clock manager.

---
 rtl/alpha_fmc_top.v | 46 ++++++++++++----------------------------------
 1 file changed, 12 insertions(+), 34 deletions(-)

diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 03c2802..1bc1ce2 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -8,7 +8,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -67,46 +67,25 @@ module alpha_fmc_top
    //----------------------------------------------------------------
    // Clock Manager
    //
-   // Clock manager is used to generate SYS_CLK from GCLK
-   // and implement the reset logic.
+   // Clock manager is used to buffer FMC_CLK and implement reset logic.
    // ----------------------------------------------------------------
-   wire               sys_clk;
-   wire               sys_rst_n;
+   wire               sys_clk;		// system clock (90 MHz)
+   wire               sys_rst_n;	// active-low reset
 
-   alpha_clkmgr #
-     (
-      .CLK_OUT_MUL      (20.0),    // 2..64
-      .CLK_OUT_DIV      (20.0)     // 1..128
-      )
-   clkmgr
-     (
-      .gclk      (gclk_pin),
-      
-      .sys_clk   (sys_clk),
-      .sys_rst_n (sys_rst_n)
-      );
-
-
-   //----------------------------------------------------------------
-   // BUFG
-   //
-   // FMC clock must be routed through the global clocking backbone.
-   // ----------------------------------------------------------------
-   wire               fmc_clk_bug;
-
-   BUFG BUFG_fmc_clk
-     (
-      .I                (fmc_clk),
-      .O                (fmc_clk_bufg)
-      );
+	alpha_clkmgr clkmgr
+	(
+		.fmc_clk		(fmc_clk),
+	
+		.sys_clk		(sys_clk),
+		.sys_rst_n		(sys_rst_n)
+	);
 
 
 
    //----------------------------------------------------------------
    // FMC Arbiter
    //
-   // FMC arbiter handles FMC access and transfers it into
-   // `sys_clk' clock domain.
+   // FMC arbiter handles FMC accesses.
    //----------------------------------------------------------------
 
    wire [23: 0]       sys_fmc_addr;     // address
@@ -121,7 +100,6 @@ module alpha_fmc_top
       )
    fmc
      (
-      .fmc_clk(fmc_clk_bufg),
       .fmc_a(fmc_a),
       .fmc_d(fmc_d),
       .fmc_ne1(fmc_ne1),
-- 
cgit v1.2.3


From f8f0e3bbe1a485fa5671b11c006df410527d2f9f Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Sat, 14 Jul 2018 18:53:32 -0400
Subject: Adjust Makefile to track source changes.

---
 build/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/build/Makefile b/build/Makefile
index 4e3a9bb..d7c18f1 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -68,8 +68,6 @@ vfiles = \
 	$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
 	$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
 	./core_selector.v \
-	$(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
-	$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
 	$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
 	$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
 	$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
-- 
cgit v1.2.3


From 297f59340bfcf4cfee141e9bedc2313fbac8b5ff Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 18 Aug 2018 02:03:14 +0300
Subject: Corrected target device.

---
 build/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/build/Makefile b/build/Makefile
index d7c18f1..f573ace 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -12,7 +12,7 @@ WORD_SIZE	:= $(shell python -c 'from struct import pack; print len(pack("L", 0))
 project		?= alpha_fmc
 vendor		= xilinx
 family		= artix7
-part		= xc7a200tfbg484-3
+part		= xc7a200tfbg484-1
 top_module	= alpha_fmc_top
 isedir		= /opt/Xilinx/14.7/ISE_DS
 xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
-- 
cgit v1.2.3


From f13b5c416776498bdb7e8722016e14aaba442bfa Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 18 Aug 2018 02:04:15 +0300
Subject: Use default synthesis options.

---
 build/xilinx.opt | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/build/xilinx.opt b/build/xilinx.opt
index 7fe9d8b..1ac8957 100644
--- a/build/xilinx.opt
+++ b/build/xilinx.opt
@@ -2,6 +2,7 @@
 -ofmt NGC
 -opt_mode speed
 -opt_level 1
+-power NO
 -iuc NO
 -keep_hierarchy no
 -netlist_hierarchy as_optimized
@@ -15,7 +16,7 @@
 -case maintain
 -slice_utilization_ratio 100
 -bram_utilization_ratio 100
-#-dsp_utilization_ratio 100
+-dsp_utilization_ratio 100
 -safe_implementation No
 -fsm_extract YES
 -fsm_encoding Auto
@@ -25,15 +26,19 @@
 -rom_extract Yes
 -rom_style Auto
 -shreg_extract YES
+-shreg_min_size 2
 -auto_bram_packing NO
 -resource_sharing YES
 -async_to_sync NO
-#-use_dsp48 auto
+-use_dsp48 auto
 -iobuf YES
--max_fanout 500
+-max_fanout 100000
+-bufg 32
 -register_duplication YES
 -register_balancing No
 -optimize_primitives NO
+-lc Auto
+-reduce_control_sets Auto
 -use_clock_enable Auto
 -use_sync_set Auto
 -use_sync_reset Auto
-- 
cgit v1.2.3


From 3abce31d6afdbbcb67b9dd5a160643a06d092861 Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Sat, 18 Aug 2018 02:08:54 +0300
Subject: 1. Disabled SmartGuide as it can thwart reproducible implementation.
 2. Enabled multi-threading for MAP and PAR, the corresponding switch is -mt. 
   MAP supports -mt off|2, PAR supports -mt off|2|3|4. Please revert back to  
  -mt off if the build system has only two cores.

---
 build/xilinx.mk | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/build/xilinx.mk b/build/xilinx.mk
index abeff7b..8c56319 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -33,8 +33,8 @@
 coregen_work_dir ?= ./coregen-tmp
 #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n
 # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk:
-map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off
-par_opts ?= -ol high
+map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off
+par_opts ?= -ol high -mt 4
 isedir ?= /opt/Xilinx/13.3/ISE_DS
 xil_env ?= . $(isedir)/settings32.sh
 flashsize ?= 8192
@@ -117,14 +117,17 @@ junk += $(project)_par.grf $(project)_par.ptwx
 junk += $(project)_par.unroutes $(project)_par.xpi
 
 $(project).ncd: $(project).ngd
-	if [ -r $(project)_par.ncd ]; then \
-		cp $(project)_par.ncd smartguide.ncd; \
-		smartguide="-smartguide smartguide.ncd"; \
-	else \
-		smartguide=""; \
-	fi; \
+	#if [ -r $(project)_par.ncd ]; then \
+	#	cp $(project)_par.ncd smartguide.ncd; \
+	#	smartguide="-smartguide smartguide.ncd"; \
+	#else \
+	#	smartguide=""; \
+	#fi; \
+	#$(xil_env); \
+	#map $(intstyle) $(map_opts) $$smartguide $<
 	$(xil_env); \
-	map $(intstyle) $(map_opts) $$smartguide $<
+	map $(intstyle) $(map_opts) $<
+
 junk += $(project).ncd $(project).pcf $(project).ngm $(project).mrp $(project).map
 junk += smartguide.ncd $(project).psr
 junk += $(project)_summary.xml $(project)_usage.xml
-- 
cgit v1.2.3


From d507f5d8174bc7ba1fce82830c61195c16f14776 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Tue, 21 Aug 2018 15:06:04 -0400
Subject: Add explicit check for timing failure, per Pavel.

---
 build/xilinx.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/build/xilinx.mk b/build/xilinx.mk
index 8c56319..b2b67ce 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -111,6 +111,7 @@ $(project)_par.ncd: $(project).ncd
 	else \
 		$(MAKE) etwr; \
 	fi
+	@ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par
 junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
 junk += $(project)_par_pad.csv $(project)_par_pad.txt
 junk += $(project)_par.grf $(project)_par.ptwx
-- 
cgit v1.2.3


From 3de07e1508c4c8f2e4fe38994cf41eabee391119 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Mon, 27 Aug 2018 11:10:19 -0400
Subject: Remove `-global_opt off` per discussion with Joachim and Pavel.

---
 build/xilinx.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/build/xilinx.mk b/build/xilinx.mk
index b2b67ce..b8ea85c 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -33,7 +33,7 @@
 coregen_work_dir ?= ./coregen-tmp
 #map_opts ?= -timing -ol high -detail -pr b -register_duplication -w -xe n
 # from https://github.com/fpga-logi/logi-hard/blob/master/build_lib/synth/xilinx.mk:
-map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off
+map_opts ?= -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt 2 -ir off -pr off -lc off -power off
 par_opts ?= -ol high -mt 4
 isedir ?= /opt/Xilinx/13.3/ISE_DS
 xil_env ?= . $(isedir)/settings32.sh
-- 
cgit v1.2.3


From 41e330bcd2eec0c9a871e82698959c742a3e8d09 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Mon, 27 Aug 2018 11:15:43 -0400
Subject: Comment smartguide out of Makefile, not just out of shell script.

---
 build/xilinx.mk | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/build/xilinx.mk b/build/xilinx.mk
index b8ea85c..e3ce440 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -118,14 +118,14 @@ junk += $(project)_par.grf $(project)_par.ptwx
 junk += $(project)_par.unroutes $(project)_par.xpi
 
 $(project).ncd: $(project).ngd
-	#if [ -r $(project)_par.ncd ]; then \
-	#	cp $(project)_par.ncd smartguide.ncd; \
-	#	smartguide="-smartguide smartguide.ncd"; \
-	#else \
-	#	smartguide=""; \
-	#fi; \
-	#$(xil_env); \
-	#map $(intstyle) $(map_opts) $$smartguide $<
+#	if [ -r $(project)_par.ncd ]; then \
+#		cp $(project)_par.ncd smartguide.ncd; \
+#		smartguide="-smartguide smartguide.ncd"; \
+#	else \
+#		smartguide=""; \
+#	fi; \
+#	$(xil_env); \
+#	map $(intstyle) $(map_opts) $$smartguide $<
 	$(xil_env); \
 	map $(intstyle) $(map_opts) $<
 
-- 
cgit v1.2.3


From f8f86f9cfbd0ac73d2b0d3600e424b9c669cea59 Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Mon, 27 Aug 2018 11:24:39 -0400
Subject: Generate detailed timing report when PAR fails.

The original version of this file appears to have been attempting to
do this, but got the grotty details wrong.
---
 build/xilinx.mk | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/build/xilinx.mk b/build/xilinx.mk
index e3ce440..9af9366 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -106,12 +106,10 @@ junk += $(project).bgn $(project).bit $(project).drc $(project)_bd.bmm
 
 $(project)_par.ncd: $(project).ncd
 	$(xil_env); \
-	if par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd; then \
-		:; \
-	else \
+	if ! par $(intstyle) $(par_opts) -w $(project).ncd $(project)_par.ncd || grep >/dev/null 'WARNING:Par:468' $(project)_par.par; then \
 		$(MAKE) etwr; \
+		exit 1; \
 	fi
-	@ ! grep >/dev/null 'WARNING:Par:468' $(project)_par.par
 junk += $(project)_par.ncd $(project)_par.par $(project)_par.pad
 junk += $(project)_par_pad.csv $(project)_par_pad.txt
 junk += $(project)_par.grf $(project)_par.ptwx
-- 
cgit v1.2.3


From 714cf340b135a2b25281a6376168b8fe57c48e6e Mon Sep 17 00:00:00 2001
From: "Pavel V. Shatov (Meister)" <meisterpaul1@yandex.ru>
Date: Thu, 6 Sep 2018 13:21:21 +0300
Subject: Constraints for 60 MHz FMC_CLK.

---
 ucf/alpha_fmc.ucf | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index efefa76..7926762 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -49,7 +49,12 @@
 # FMC_CLK Timing (can be up to 90 MHz)
 #-------------------------------------------------------------------------------
 NET  "fmc_clk" TNM_NET = TNM_fmc_clk;
-TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%;
+
+# 90 MHz
+#TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%;
+
+# 60 MHz
+TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 16.667 ns HIGH 50%;
 
 
 #-------------------------------------------------------------------------------
-- 
cgit v1.2.3


From f01086416f290352c2c9faa0f1c6b1fce31e8f01 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Mon, 14 Jan 2019 17:39:47 -0500
Subject: Add include directives for Pavel's .vh files.

---
 build/xilinx.opt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/build/xilinx.opt b/build/xilinx.opt
index 1ac8957..933f7df 100644
--- a/build/xilinx.opt
+++ b/build/xilinx.opt
@@ -45,3 +45,4 @@
 -iob auto
 -equivalent_register_removal YES
 -slice_utilization_ratio_maxmargin 5
+-vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode}
-- 
cgit v1.2.3


From 516b2975958b05c72f573c37c075e5793c514101 Mon Sep 17 00:00:00 2001
From: Paul Selkirk <paul@psgd.org>
Date: Tue, 22 Jan 2019 19:39:09 -0500
Subject: Upon reflection, I prefer the way Pavel handled include paths in
 8cd28d0 (which he only committed on fmc_clk, and I was only looking at
 master).

But I moved the curly brackets from Makefile to xilinx.mk, because
a) Makefile shouldn't need to know the picky details of xst option
syntax, and
b) xst will throw an uninformative error if called with '-vlgincdir '
versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile.
---
 build/Makefile   | 4 ++++
 build/xilinx.mk  | 1 +
 build/xilinx.opt | 1 -
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/build/Makefile b/build/Makefile
index f573ace..60e55f9 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir		= /opt/Xilinx/14.7/ISE_DS
 xil_env		= . $(isedir)/settings$(WORD_SIZE).sh
 ucf		?= ../ucf/$(project).ucf
 
+# Verilog include directories, if needed
+
+vlgincdir	= $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
 all:	$(project).bit
 
 # Build the default core_selector if it doesn't already exist.
diff --git a/build/xilinx.mk b/build/xilinx.mk
index 9af9366..4bfefde 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -154,6 +154,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
 	echo "-top $(top_module)" >> $@
 	echo "-ifn $(project).prj" >> $@
 	echo "-ofn $(project).ngc" >> $@
+	echo "-vlgincdir {$(vlgincdir)}" >> $@
 	cat ./xilinx.opt $(optfile) >> $@
 junk += $(project).scr
 
diff --git a/build/xilinx.opt b/build/xilinx.opt
index 933f7df..1ac8957 100644
--- a/build/xilinx.opt
+++ b/build/xilinx.opt
@@ -45,4 +45,3 @@
 -iob auto
 -equivalent_register_removal YES
 -slice_utilization_ratio_maxmargin 5
--vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode}
-- 
cgit v1.2.3