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2018-06-21Fixed bad mistake on reset signal. Minor cleanup.Joachim Strömbergson
2018-06-14(1) Added ports and constraints for the gpio banks connected to the FPGA. ↵Joachim Strömbergson
(2) Added toggle circuit that generates a divided down version of the internal sys_clk. This divided clock is presented on pin 0 of both gpio banks.
2017-09-21Separate FMC test from mainline top-level module.Paul Selkirk
2016-06-14Move core config script here from core/platform/common, and adapt to the ↵Paul Selkirk
larger fmc address bus.
2016-05-18add mkmif supportPaul Selkirk
2016-05-16Ported Cryptech platform to the Alpha board.Pavel V. Shatov (Meister)
2016-05-12Initial commit, based on core/platform/novena[/fmc], probably doesn't work, ↵Paul Selkirk
but gives Pavel and Fredrik a place to put their stuff.