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-rw-r--r--ucf/alpha_fmc.ucf169
1 files changed, 85 insertions, 84 deletions
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index b323104..34b2072 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -3,11 +3,11 @@
# alpha_fmc.ucf
# -------------------
# Constraint file for implementing the Cryptech Alpha base
-# for the Xilinx Spartan6 LX45 on the Alpha.
+# for the Xilinx Artix-7 200T on the Alpha.
#
#
# Author: Pavel Shatov
-# Copyright (c) 2014, NORDUnet A/S All rights reserved.
+# Copyright (c) 2016, NORDUnet A/S All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -37,15 +37,11 @@
#
#======================================================================
-#-------------------------------------------------------------------------------
-CONFIG VCCAUX = 3.3;
-#-------------------------------------------------------------------------------
-
#--------------------------------------------------------------------------------
# GCLK Timing (fixed at 50 MHz)
#--------------------------------------------------------------------------------
-NET "gclk_p_pin" TNM_NET = TNM_gclk;
+NET "gclk_pin" TNM_NET = TNM_gclk;
TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
@@ -59,81 +55,86 @@ TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
#-------------------------------------------------------------------------------
# FPGA Pinout
#-------------------------------------------------------------------------------
-NET "led_pin" LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
-NET "apoptosis_pin" LOC = "K1" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
-NET "reset_mcu_b_pin" LOC = "F1" | IOSTANDARD = "LVCMOS33" | PULLUP;
-#
-NET "gclk_p_pin" LOC = "H2" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";
-NET "gclk_n_pin" LOC = "H1" | IOSTANDARD = "LVDS_25" | DIFF_TERM = "TRUE";
-#
-NET "fmc_clk" LOC = "T8" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_ne1" LOC = "R7" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_noe" LOC = "R8" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_nwe" LOC = "V11" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_nl" LOC = "T7" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_nwait" LOC = "V8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-#
-NET "fmc_a<0>" LOC = "V7" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<1>" LOC = "M5" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<2>" LOC = "L4" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<3>" LOC = "M3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<4>" LOC = "L3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<5>" LOC = "P2" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<6>" LOC = "K3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<7>" LOC = "K4" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<8>" LOC = "R3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<9>" LOC = "T3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<10>" LOC = "V4" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<11>" LOC = "T4" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<12>" LOC = "J3" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<13>" LOC = "J1" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<14>" LOC = "J6" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<15>" LOC = "U16" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<16>" LOC = "M1" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<17>" LOC = "F2" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<18>" LOC = "R11" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<19>" LOC = "V5" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<20>" LOC = "G1" | IOSTANDARD = "LVCMOS33" ;
-NET "fmc_a<21>" LOC = "T2" | IOSTANDARD = "LVCMOS33" ;
-#NET "fmc_a<22>" LOC = " " | IOSTANDARD = "LVCMOS33" ;
-#NET "fmc_a<23>" LOC = " " | IOSTANDARD = "LVCMOS33" ;
-#NET "fmc_a<24>" LOC = " " | IOSTANDARD = "LVCMOS33" ;
-#NET "fmc_a<25>" LOC = " " | IOSTANDARD = "LVCMOS33" ;
-#
-NET "fmc_d<0>" LOC = "K2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<3>" LOC = "T9" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<4>" LOC = "T5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<5>" LOC = "R5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<6>" LOC = "T10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<7>" LOC = "R10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<8>" LOC = "P6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<9>" LOC = "N5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<10>" LOC = "V10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<11>" LOC = "U10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<12>" LOC = "L5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<13>" LOC = "K6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<14>" LOC = "H4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<15>" LOC = "H3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<16>" LOC = "K5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<17>" LOC = "L2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<18>" LOC = "L1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<19>" LOC = "L7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<20>" LOC = "T11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<21>" LOC = "T14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<22>" LOC = "V14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<23>" LOC = "L6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<24>" LOC = "U13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<25>" LOC = "V13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<26>" LOC = "U11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<27>" LOC = "U8" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<28>" LOC = "V6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<29>" LOC = "T6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<30>" LOC = "U5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-NET "fmc_d<31>" LOC = "U7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
-
-NET "ct_noise" LOC = "H7" | IOSTANDARD = "LVCMOS33" ;
+#
+NET "led_pins<0>" LOC = "U3";
+NET "led_pins<1>" LOC = "T1";
+NET "led_pins<2>" LOC = "W22";
+NET "led_pins<3>" LOC = "AA20";
+#
+NET "led_pins<*>" IOSTANDARD = "LVCMOS33";
+NET "led_pins<*>" SLEW = SLOW;
+NET "led_pins<*>" DRIVE = 8;
+#
+NET "gclk_pin" LOC = "D17" | IOSTANDARD = "LVCMOS33" ;
+#
+NET "fmc_clk" LOC = "W11" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_ne1" LOC = "V5" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_noe" LOC = "W16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nwe" LOC = "AA6" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nl" LOC = "W17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_nwait" LOC = "Y6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+#
+NET "fmc_a<0>" LOC = "Y17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<1>" LOC = "AB16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<2>" LOC = "AA16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<3>" LOC = "Y16" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<4>" LOC = "AB17" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<5>" LOC = "AA13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<6>" LOC = "AB13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<7>" LOC = "AA15" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<8>" LOC = "AB15" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<9>" LOC = "Y13" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<10>" LOC = "AA14" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<11>" LOC = "Y14" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<12>" LOC = "AB10" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<13>" LOC = "V2" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<14>" LOC = "AB12" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<15>" LOC = "AB8" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<16>" LOC = "AA9" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<17>" LOC = "AA8" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<18>" LOC = "Y7" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<19>" LOC = "AB21" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<20>" LOC = "AB22" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<21>" LOC = "AB20" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<22>" LOC = "Y21" | IOSTANDARD = "LVCMOS33" ;
+NET "fmc_a<23>" LOC = "Y22" | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<24>" LOC = "AB18" | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<25>" LOC = "AA19" | IOSTANDARD = "LVCMOS33" ;
+#
+NET "fmc_d<0>" LOC = "AB7" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<1>" LOC = "AB6" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<2>" LOC = "U1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<3>" LOC = "U2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<4>" LOC = "AB11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<5>" LOC = "AA11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<6>" LOC = "Y11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<7>" LOC = "Y12" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<8>" LOC = "Y18" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<9>" LOC = "AA21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<10>" LOC = "W20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<11>" LOC = "N15" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<12>" LOC = "U20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<13>" LOC = "AA1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<14>" LOC = "AB1" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<15>" LOC = "AB2" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<16>" LOC = "AB3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<17>" LOC = "Y3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<18>" LOC = "AA3" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<19>" LOC = "AA5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<20>" LOC = "AB5" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<21>" LOC = "Y4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<22>" LOC = "AA4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<23>" LOC = "V4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<24>" LOC = "W10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<25>" LOC = "R4" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<26>" LOC = "W12" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<27>" LOC = "W14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<28>" LOC = "V20" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<29>" LOC = "V18" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<30>" LOC = "R21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET "fmc_d<31>" LOC = "P21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+
+NET "ct_noise" LOC = "W19" | IOSTANDARD = "LVCMOS33" ;
#-------------------------------------------------------------------------------
# FMC Input Timing
@@ -143,7 +144,7 @@ NET "ct_noise" LOC = "H7" | IOSTANDARD = "LVCMOS33" ;
# datasheet. Control signals NE1, NL and NWE all have different timing values.
# Instead of writing individual constraints for every control signal, the most
# strict constraint is applied to all control signals. This should not cause
-# any P&R issues, since Spartan-6 can handle 90 MHz easily.
+# any P&R issues, since Spartan-6 (and Artix-7) can handle 90 MHz easily.
#
# NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
#
@@ -174,7 +175,7 @@ TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk"
NET "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
-TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 11.5 ns AFTER "fmc_clk" FALLING;
+TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 16.7 ns AFTER "fmc_clk" FALLING;
#-------------------------------------------------------------------------------
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 08:00:53 +0000