diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/alpha_fmc_top.v | 76 |
1 files changed, 66 insertions, 10 deletions
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v index 03c2802..a86a2c6 100644 --- a/rtl/alpha_fmc_top.v +++ b/rtl/alpha_fmc_top.v @@ -60,11 +60,19 @@ module alpha_fmc_top input wire mkm_do, output wire mkm_di, + output wire [7: 0] gpio_a, + output wire [7: 0] gpio_b, output wire [3: 0] led_pins // {red, yellow, green, blue} ); //---------------------------------------------------------------- + // Dummy assignments to bypass unconnected outpins pins check in BitGen + //---------------------------------------------------------------- + assign led_pins[3:1] = 3'b000; + + + //---------------------------------------------------------------- // Clock Manager // // Clock manager is used to generate SYS_CLK from GCLK @@ -81,7 +89,7 @@ module alpha_fmc_top clkmgr ( .gclk (gclk_pin), - + .sys_clk (sys_clk), .sys_rst_n (sys_rst_n) ); @@ -179,14 +187,62 @@ module alpha_fmc_top .mkm_cs_n(mkm_cs_n), .mkm_do(mkm_do), .mkm_di(mkm_di) - ); - - - // - // Dummy assignment to bypass unconnected outpins pins check in BitGen - // - - assign led_pins[3:1] = 3'b000; + ); -endmodule + //---------------------------------------------------------------- + // sys_clk_toggle + // + // Simple circuit that allows observation of the sys_clk on + // an output pin. The sys_clk is divided down to allow + // measurement with simple equipment. + // + // One toggle cycle will be 2 * TOGGLE_DELAY_CYCLES. The + // number of cycles are selected to generate a 500 kHz period + // when sys_clk is running at 50 MHz. + // + // The toggle signal is presented at pin 0 of both GPIO banks + // available to the FPGA on the Alpha board. + //---------------------------------------------------------------- + localparam TOGGLE_DELAY_CYCLES = 50; + + reg [15 : 0] toggle_ctr_reg; + reg [15 : 0] toggle_ctr_new; + + reg toggle_reg; + reg toggle_we; + + assign gpio_a = {7'b0101010, toggle_reg}; + assign gpio_b = {7'b1010101, toggle_reg}; + + always @(posedge sys_clk) + begin: sys_clk_toggle_reg_update + if (!reset_n) + begin + toggle_ctr_reg <= 16'h0; + toggle_reg <= 1'b0; + end + else + begin + toggle_ctr_reg <= toggle_ctr_new; + + if (toggle_we) + toggle_reg <= ~toggle_reg; + end + end + + always @* + begin : sys_clk_toggle + if (toggle_ctr_reg == TOGGLE_DELAY_CYCLES) + begin + toggle_ctr_new = 16'h0; + toggle_we = 1'b1; + end + else + begin + toggle_ctr_new = toggle_ctr_reg + 1'b1; + toggle_we = 1'b0; + end + end + +endmodule // alpha_fmc_top |