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-rw-r--r--rtl/alpha_clkmgr.v38
1 files changed, 24 insertions, 14 deletions
diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v
index f870a75..5c4099e 100644
--- a/rtl/alpha_clkmgr.v
+++ b/rtl/alpha_clkmgr.v
@@ -7,7 +7,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -39,19 +39,28 @@
module alpha_clkmgr
(
- input wire gclk, // signal from clock pin
+ input wire fmc_clk, // signal from clock pin
- output wire sys_clk, // buffered system clock output
+ output wire sys_clk, // buffered system clock output
output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
//
- // Parameters
- //
- parameter CLK_OUT_MUL = 20.0;
- parameter CLK_OUT_DIV = 20.0;
-
+ // Settings
+ //
+
+ /*
+ * fmc_clk is 90 MHz, sys_clk is also 90 MHz routed through an MMCM.
+ *
+ * VCO frequency is 1080 MHz.
+ *
+ */
+ localparam CLK_OUT_MUL = 12.0;
+ localparam CLK_OUT_DIV = 12.0;
+ localparam CLK_OUT_PHI = 45.0;
+
+
//
// Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
//
@@ -63,21 +72,22 @@ module alpha_clkmgr
clkmgr_mmcm #
(
- .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64
- .CLK_OUT_DIV (CLK_OUT_DIV) // 1..128
+ .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64
+ .CLK_OUT_DIV (CLK_OUT_DIV), // 1..128
+ .CLK_OUT_PHI (CLK_OUT_PHI) // 0.0..360.0
)
mmcm
(
- .clk_in (gclk),
+ .gclk_in (fmc_clk),
.reset_in (mmcm_reset),
.gclk_out (gclk_int),
.gclk_missing_out (gclk_missing),
- .clk_out (sys_clk),
+ .clk_out (sys_clk),
.clk_valid_out (mmcm_locked)
);
-
+
//
@@ -93,7 +103,7 @@ module alpha_clkmgr
always @(posedge gclk_int or posedge gclk_missing)
//
- if ((gclk_missing == 1'b1))
+ if (gclk_missing == 1'b1)
mmcm_rst_shreg <= {16{1'b1}};
else
mmcm_rst_shreg <= {mmcm_rst_shreg[14:0], 1'b0};