diff options
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/clkmgr_mmcm.v | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/rtl/clkmgr_mmcm.v b/rtl/clkmgr_mmcm.v index 852288b..03b0747 100644 --- a/rtl/clkmgr_mmcm.v +++ b/rtl/clkmgr_mmcm.v @@ -6,7 +6,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2016, NORDUnet A/S All rights reserved. +// Copyright (c) 2016, 2018, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -38,22 +38,23 @@ module clkmgr_mmcm ( - input wire clk_in, + input wire gclk_in, input wire reset_in, output wire gclk_out, output wire gclk_missing_out, - output wire clk_out, + output wire clk_out,
output wire clk_valid_out ); - // - // Parameters - // - parameter CLK_OUT_MUL = 20.0; // multiply factor for output clock frequency (2..64) - parameter CLK_OUT_DIV = 20.0; // divide factor for output clock frequency (1..128) + // + // Parameters + // + parameter CLK_OUT_MUL = 12.0; // multiply factor for output clock frequency (2..64) + parameter CLK_OUT_DIV = 12.0; // divide factor for output clock frequency (1..128)
+ parameter CLK_OUT_PHI = 45.0; // clock phase shift (0.0..360.0)
// @@ -61,12 +62,12 @@ module clkmgr_mmcm // (* BUFFER_TYPE="NONE" *) - wire clk_in_ibufg;
+ wire gclk_in_ibufg;
IBUFG IBUFG_gclk
(
- .I (clk_in),
- .O (clk_in_ibufg)
+ .I (gclk_in),
+ .O (gclk_in_ibufg)
);
@@ -80,7 +81,7 @@ module clkmgr_mmcm MMCME2_ADV #
(
- .CLKIN1_PERIOD (20.000),
+ .CLKIN1_PERIOD (11.111),
.REF_JITTER1 (0.010),
.STARTUP_WAIT ("FALSE"),
@@ -94,7 +95,7 @@ module clkmgr_mmcm .CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLK_OUT_DIV),
- .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_PHASE (CLK_OUT_PHI),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT0_DUTY_CYCLE (0.500),
@@ -102,7 +103,7 @@ module clkmgr_mmcm )
MMCME2_ADV_inst
(
- .CLKIN1 (clk_in_ibufg),
+ .CLKIN1 (gclk_in_ibufg),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
@@ -151,7 +152,7 @@ module clkmgr_mmcm // // Mapping // - assign gclk_out = clk_in_ibufg; + assign gclk_out = gclk_in_ibufg; assign clk_valid_out = mmcm_locked; |