diff options
Diffstat (limited to 'rtl/alpha_fmc_top.v')
| -rw-r--r-- | rtl/alpha_fmc_top.v | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v index 79bfba8..03c2802 100644 --- a/rtl/alpha_fmc_top.v +++ b/rtl/alpha_fmc_top.v @@ -108,17 +108,12 @@ module alpha_fmc_top // FMC arbiter handles FMC access and transfers it into // `sys_clk' clock domain. //---------------------------------------------------------------- - //`define test wire [23: 0] sys_fmc_addr; // address wire sys_fmc_wren; // write enable wire sys_fmc_rden; // read enable wire [31: 0] sys_fmc_dout; // data output (from STM32 to FPGA) -`ifdef test - reg [31: 0] sys_fmc_din; // data input (from FPGA to STM32) -`else wire [31: 0] sys_fmc_din; // data input (from FPGA to STM32) -`endif fmc_arbiter # ( @@ -160,69 +155,6 @@ module alpha_fmc_top ); -`ifdef test - //---------------------------------------------------------------- - // Dummy Register - // - // General-purpose register to test FMC interface using STM32 - // demo program instead of core selector logic. - // - // This register is a bit tricky, but it allows testing of both - // data and address buses. Reading from FPGA will always return - // value, which is currently stored in the test register, - // regardless of read transaction address. Writing to FPGA has - // two variants: a) writing to address 0 will store output data - // data value in the test register, b) writing to any non-zero - // address will store _address_ of write transaction in the test - // register. - // - // To test data bus, write some different patterns to address 0, - // then readback from any address and compare. - // - // To test address bus, write anything to some different non-zero - // addresses, then readback from any address and compare returned - // value with previously written address. - // - //---------------------------------------------------------------- - reg [31: 0] test_reg; - - - - // - // Noise Capture Register - // - reg [31: 0] noise_reg; - - always @(posedge sys_clk) - // - noise_reg <= {noise_reg[30:0], ct_noise}; - - - - always @(posedge sys_clk) - // - if (sys_fmc_wren) begin - // - // when writing to address 0, store input data value - // - // when writing to non-zero address, store _address_ - // (padded with zeroes) instead of data - // - test_reg <= (sys_fmc_addr == {24{1'b0}}) ? sys_fmc_dout : {{8{1'b0}}, sys_fmc_addr}; - // - end else if (sys_fmc_rden) begin - // - // always return current value, ignore address - // - sys_fmc_din <= (sys_fmc_addr == {24{1'b1}}) ? noise_reg : test_reg; - - // when reading from address 0, return the current value - // when reading from other addresses, return the address - //sys_fmc_din <= (sys_fmc_addr == {22{1'b0}}) ? test_reg : {{10{1'b0}}, sys_fmc_addr}; - // - end - -`else // !`ifdef test //---------------------------------------------------------------- // Core Selector // @@ -248,7 +180,6 @@ module alpha_fmc_top .mkm_do(mkm_do), .mkm_di(mkm_di) ); -`endif // |