diff options
Diffstat (limited to 'rtl/alpha_fmc_top.v')
| -rw-r--r-- | rtl/alpha_fmc_top.v | 82 |
1 files changed, 43 insertions, 39 deletions
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v index b5b85f6..e829545 100644 --- a/rtl/alpha_fmc_top.v +++ b/rtl/alpha_fmc_top.v @@ -3,12 +3,12 @@ // alpha_top.v // ------------ // Top module for the Cryptech Alpha FPGA framework. This design -// allow us to run the EIM interface at one clock and cores including +// allow us to run the FMC interface at one clock and cores including // core selector with the always present global clock. // // // Author: Pavel Shatov -// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// Copyright (c) 2016, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -42,16 +42,12 @@ module alpha_fmc_top ( - input wire gclk_p_pin, - input wire gclk_n_pin, + input wire gclk_pin, // 50 MHz - input wire reset_mcu_b_pin, - - // Cryptech avalanche noise board input - input wire ct_noise, + input wire ct_noise, // cryptech avalanche noise circuit input wire fmc_clk, // clock - input wire [21: 0] fmc_a, // address + input wire [23: 0] fmc_a, // address inout wire [31: 0] fmc_d, // data input wire fmc_ne1, // chip select input wire fmc_noe, // output enable @@ -59,8 +55,7 @@ module alpha_fmc_top input wire fmc_nl, // latch enable output wire fmc_nwait,// wait - output wire apoptosis_pin, - output wire led_pin + output wire [3: 0] led_pins // {red, yellow, green, blue} ); @@ -75,24 +70,23 @@ module alpha_fmc_top alpha_clkmgr # ( - .CLK_OUT_MUL (2), // 2..32 - .CLK_OUT_DIV (2) // 1..32 + .CLK_OUT_MUL (20.0), // 2..64 + .CLK_OUT_DIV (20.0) // 1..128 ) clkmgr ( - .gclk_p (gclk_p_pin), - .gclk_n (gclk_n_pin), - - .reset_mcu_b (reset_mcu_b_pin), - - .sys_clk (sys_clk), - .sys_rst_n (sys_rst_n) + .gclk (gclk_pin),
+ + .sys_clk (sys_clk), + .sys_rst_n (sys_rst_n) ); - // + //---------------------------------------------------------------- // BUFG // + // FMC clock must be routed through the global clocking backbone. + // ---------------------------------------------------------------- wire fmc_clk_bug; BUFG BUFG_fmc_clk @@ -109,8 +103,9 @@ module alpha_fmc_top // FMC arbiter handles FMC access and transfers it into // `sys_clk' clock domain. //---------------------------------------------------------------- +`define test
- wire [21: 0] sys_fmc_addr; // address + wire [23: 0] sys_fmc_addr; // address wire sys_fmc_wren; // write enable wire sys_fmc_rden; // read enable wire [31: 0] sys_fmc_dout; // data output (from STM32 to FPGA) @@ -122,7 +117,7 @@ module alpha_fmc_top fmc_arbiter # ( - .NUM_ADDR_BITS(22) // change to 26 when + .NUM_ADDR_BITS(24) // change to 26 when Alpha is alive! ) fmc ( @@ -156,7 +151,7 @@ module alpha_fmc_top .sys_clk(sys_clk), .sys_rst_n(sys_rst_n), .fmc_active(sys_fmc_wren | sys_fmc_rden), - .led_out(led_pin) + .led_out(led_pins[0]) ); @@ -185,7 +180,20 @@ module alpha_fmc_top // //---------------------------------------------------------------- reg [31: 0] test_reg; - +
+
+
+ //
+ // Noise Capture Register
+ //
+ reg [31: 0] noise_reg;
+
+ always @(posedge sys_clk)
+ //
+ noise_reg <= {noise_reg[30:0], ct_noise};
+
+
+ always @(posedge sys_clk) // if (sys_fmc_wren) begin @@ -195,13 +203,13 @@ module alpha_fmc_top // when writing to non-zero address, store _address_ // (padded with zeroes) instead of data // - test_reg <= (sys_fmc_addr == {22{1'b0}}) ? sys_fmc_dout : {{10{1'b0}}, sys_fmc_addr}; + test_reg <= (sys_fmc_addr == {24{1'b0}}) ? sys_fmc_dout : {{8{1'b0}}, sys_fmc_addr}; // end else if (sys_fmc_rden) begin // // always return current value, ignore address // - sys_fmc_din <= test_reg; + sys_fmc_din <= (sys_fmc_addr == {24{1'b1}}) ? noise_reg : test_reg; // when reading from address 0, return the current value // when reading from other addresses, return the address @@ -230,18 +238,14 @@ module alpha_fmc_top .noise(ct_noise) ); -`endif - - - //---------------------------------------------------------------- - // Alpha Patch - // - // Patch logic to keep the Alpha board happy. - // The apoptosis_pin pin must be kept low or the whole board - // (more exactly the CPU) will be reset after the FPGA has - // been configured. - //---------------------------------------------------------------- - assign apoptosis_pin = 1'b0; +`endif
+
+
+ //
+ // Dummy assignment to bypass unconnected outpins pins check in BitGen
+ //
+
+ assign led_pins[3:1] = 3'b000; endmodule |