diff options
Diffstat (limited to 'rtl/alpha_clkmgr.v')
| -rw-r--r-- | rtl/alpha_clkmgr.v | 69 |
1 files changed, 33 insertions, 36 deletions
diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v index 1cc0337..f870a75 100644 --- a/rtl/alpha_clkmgr.v +++ b/rtl/alpha_clkmgr.v @@ -7,7 +7,7 @@ // // // Author: Pavel Shatov -// Copyright (c) 2015, NORDUnet A/S All rights reserved. +// Copyright (c) 2016, NORDUnet A/S All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions @@ -39,10 +39,7 @@ module alpha_clkmgr ( - input wire gclk_p, // signal from clock pins - input wire gclk_n, // - - input wire reset_mcu_b, // cpu reset (async, active-low) + input wire gclk, // signal from clock pin output wire sys_clk, // buffered system clock output output wire sys_rst_n // system reset output (async set, sync clear, active-low) @@ -52,74 +49,74 @@ module alpha_clkmgr // // Parameters // - parameter CLK_OUT_MUL = 2; - parameter CLK_OUT_DIV = 2; + parameter CLK_OUT_MUL = 20.0; + parameter CLK_OUT_DIV = 20.0; // - // Wrapper for Xilinx-specific DCM (Digital Clock Manager) primitive. + // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive. // - wire gclk; // buffered input clock - wire dcm_reset; // dcm reset - wire dcm_locked; // output clock valid - wire gclk_missing; // no input clock + wire gclk_int; // buffered input clock + wire mmcm_reset; // reset input + wire mmcm_locked; // output clock valid + wire gclk_missing; // input clock stopped
- clkmgr_dcm # + clkmgr_mmcm # ( - .CLK_OUT_MUL (CLK_OUT_MUL), - .CLK_OUT_DIV (CLK_OUT_DIV) + .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64 + .CLK_OUT_DIV (CLK_OUT_DIV) // 1..128 ) - dcm + mmcm ( - .clk_in_p (gclk_p), - .clk_in_n (gclk_n), - .reset_in (dcm_reset), + .clk_in (gclk), + .reset_in (mmcm_reset), - .gclk_out (gclk), + .gclk_out (gclk_int), .gclk_missing_out (gclk_missing), .clk_out (sys_clk), - .clk_valid_out (dcm_locked) - ); + .clk_valid_out (mmcm_locked) + );
+ // - // DCM Reset Logic + // MMCM Reset Logic // - /* DCM should be reset on power-up, when input clock is stopped or when the - * CPU gets reset. Note that DCM requires active-high reset, so the shift - * register is preloaded with 1's and gradually filled with 0's. + /* MMCM should be reset on power-up and when the input clock is stopped.
+ * Note that MMCM requires active-high reset, so the shift register is
+ * preloaded with 1's and then gradually filled with 0's. */ - reg [15: 0] dcm_rst_shreg = {16{1'b1}}; // 16-bit shift register + reg [15: 0] mmcm_rst_shreg = {16{1'b1}}; // 16-bit shift register - always @(posedge gclk or negedge reset_mcu_b or posedge gclk_missing) + always @(posedge gclk_int or posedge gclk_missing) // - if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1)) - dcm_rst_shreg <= {16{1'b1}}; + if ((gclk_missing == 1'b1)) + mmcm_rst_shreg <= {16{1'b1}}; else - dcm_rst_shreg <= {dcm_rst_shreg[14:0], 1'b0}; + mmcm_rst_shreg <= {mmcm_rst_shreg[14:0], 1'b0}; - assign dcm_reset = dcm_rst_shreg[15]; + assign mmcm_reset = mmcm_rst_shreg[15]; // // System Reset Logic // - /* System reset is asserted for 16 cycles whenever DCM aquires lock. Note + /* System reset is asserted for 16 cycles whenever MMCM aquires lock. Note * that system reset is active-low, so the shift register is preloaded with * 0's and gradually filled with 1's. */ reg [15: 0] sys_rst_shreg = {16{1'b0}}; // 16-bit shift register - always @(posedge sys_clk or negedge reset_mcu_b or posedge gclk_missing or negedge dcm_locked) + always @(posedge sys_clk or posedge gclk_missing or negedge mmcm_locked) // - if ((reset_mcu_b == 1'b0) || (gclk_missing == 1'b1) || (dcm_locked == 1'b0)) + if ((gclk_missing == 1'b1) || (mmcm_locked == 1'b0)) sys_rst_shreg <= {16{1'b0}}; - else if (dcm_locked == 1'b1) + else if (mmcm_locked == 1'b1) sys_rst_shreg <= {sys_rst_shreg[14:0], 1'b1}; assign sys_rst_n = sys_rst_shreg[15]; |