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-rw-r--r--build/Makefile8
-rw-r--r--build/Makefile.test49
2 files changed, 55 insertions, 2 deletions
diff --git a/build/Makefile b/build/Makefile
index 763ad5e..4e3a9bb 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -25,10 +25,10 @@ all: $(project).bit
CONFIG = $(CORE_TREE)/platform/common/config
CONFIG_BOARD = alpha
CONFIG_PROJECT = hsm
-CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD) -p $(CONFIG_PROJECT)
+CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD)
core_selector.v core_vfiles.mk:
- $(CONFIG_GEN)
+ $(CONFIG_GEN) -p $(CONFIG_PROJECT)
# Build some different configurations
@@ -56,6 +56,10 @@ hsm:
$(CONFIG_GEN) -p hsm
$(MAKE) project=$(project)_hsm ucf=$(ucf)
+hsm-super:
+ $(CONFIG_GEN) -p hsm-super
+ $(MAKE) project=$(project)_hsm-super ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \
diff --git a/build/Makefile.test b/build/Makefile.test
new file mode 100644
index 0000000..7243bd5
--- /dev/null
+++ b/build/Makefile.test
@@ -0,0 +1,49 @@
+# Localize all the relative path awfulness in one variable.
+
+CORE_TREE := $(abspath ../../..)
+
+# Figure out what the native word size is on the build host, because
+# the XiLinx tools care for some reason.
+
+WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) * 8')
+
+# Parameters to xilinx.mk.
+
+project ?= alpha_fmc_test
+vendor = xilinx
+family = artix7
+part = xc7a200tfbg484-3
+top_module = alpha_fmc_top
+isedir = /opt/Xilinx/14.7/ISE_DS
+xil_env = . $(isedir)/settings$(WORD_SIZE).sh
+ucf ?= ../ucf/$(project).ucf
+
+all: $(project).bit
+
+# Verilog files that always go with builds on this platform.
+
+vfiles = \
+ $(CORE_TREE)/platform/alpha/rtl/alpha_fmc_test.v \
+ $(CORE_TREE)/platform/alpha/rtl/alpha_regs.v \
+ $(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
+ $(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
+ $(CORE_TREE)/comm/fmc/src/rtl/fmc_regs.v
+
+include xilinx.mk
+
+# 'clean' target collects files by project name, and we just broke that
+# by adding configurations
+
+junk += *.bgn *.bit *.bld *.cfi *.drc *.lso *.map *.mcs *.mrp *.ncd *.ngc \
+ *.ngd *.ngm *.pcf *.post_map.twr *.post_map.twx *.prj *.prm *.psr \
+ *.scr *.srp *.twr *.twx *_bd.bmm *_bitgen.xwb *_bitgen.xwbt \
+ *_err.twr *_err.twx *_par.grf *_par.ncd *_par.pad *_par.par \
+ *_par.ptwx *_par.unroutes *_par.xpi *_par_pad.csv *_par_pad.txt \
+ *_summary.xml *_usage.xml
+
+distclean: clean