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-rw-r--r--build/Makefile18
1 files changed, 11 insertions, 7 deletions
diff --git a/build/Makefile b/build/Makefile
index aed01df..d5d4871 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -22,32 +22,36 @@ all: $(project).bit
# Build the default core_selector if it doesn't already exist.
-CONFIG = $(CORE_TREE)/platform/common/config
+CONFIG = .
core_selector.v core_vfiles.mk:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg
+ $(CONFIG)/config.py
# Build some different configurations
bare:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s bare
+ $(CONFIG)/config.py -s bare
$(MAKE) project=$(project)_bare ucf=$(ucf)
trng:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s trng
+ $(CONFIG)/config.py -s trng
$(MAKE) project=$(project)_trng ucf=$(ucf)
hash:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s hash
+ $(CONFIG)/config.py -s hash
$(MAKE) project=$(project)_hash ucf=$(ucf)
rsa:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa
+ $(CONFIG)/config.py -s rsa
$(MAKE) project=$(project)_rsa ucf=$(ucf)
mkmif:
- $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s mkmif
+ $(CONFIG)/config.py -s mkmif
$(MAKE) project=$(project)_mkmif ucf=$(ucf)
+hsm:
+ $(CONFIG)/config.py -s hsm
+ $(MAKE) project=$(project)_hsm ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \