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-rw-r--r--build/Makefile8
1 files changed, 6 insertions, 2 deletions
diff --git a/build/Makefile b/build/Makefile
index 763ad5e..4e3a9bb 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -25,10 +25,10 @@ all: $(project).bit
CONFIG = $(CORE_TREE)/platform/common/config
CONFIG_BOARD = alpha
CONFIG_PROJECT = hsm
-CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD) -p $(CONFIG_PROJECT)
+CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b $(CONFIG_BOARD)
core_selector.v core_vfiles.mk:
- $(CONFIG_GEN)
+ $(CONFIG_GEN) -p $(CONFIG_PROJECT)
# Build some different configurations
@@ -56,6 +56,10 @@ hsm:
$(CONFIG_GEN) -p hsm
$(MAKE) project=$(project)_hsm ucf=$(ucf)
+hsm-super:
+ $(CONFIG_GEN) -p hsm-super
+ $(MAKE) project=$(project)_hsm-super ucf=$(ucf)
+
# Verilog files that always go with builds on this platform.
vfiles = \