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-rw-r--r--build/Makefile17
1 files changed, 9 insertions, 8 deletions
diff --git a/build/Makefile b/build/Makefile
index d5d4871..9f46771 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -22,34 +22,35 @@ all: $(project).bit
# Build the default core_selector if it doesn't already exist.
-CONFIG = .
+CONFIG = $(CORE_TREE)/platform/common/config
+CONFIG_GEN = $(CONFIG)/core_config.py -c $(CONFIG)/core.cfg -b alpha
core_selector.v core_vfiles.mk:
- $(CONFIG)/config.py
+ $(CONFIG_GEN)
# Build some different configurations
bare:
- $(CONFIG)/config.py -s bare
+ $(CONFIG_GEN) -p bare
$(MAKE) project=$(project)_bare ucf=$(ucf)
trng:
- $(CONFIG)/config.py -s trng
+ $(CONFIG_GEN) -p trng
$(MAKE) project=$(project)_trng ucf=$(ucf)
hash:
- $(CONFIG)/config.py -s hash
+ $(CONFIG_GEN) -p hash
$(MAKE) project=$(project)_hash ucf=$(ucf)
rsa:
- $(CONFIG)/config.py -s rsa
+ $(CONFIG_GEN) -p rsa
$(MAKE) project=$(project)_rsa ucf=$(ucf)
mkmif:
- $(CONFIG)/config.py -s mkmif
+ $(CONFIG_GEN) -p mkmif
$(MAKE) project=$(project)_mkmif ucf=$(ucf)
hsm:
- $(CONFIG)/config.py -s hsm
+ $(CONFIG_GEN) -p hsm
$(MAKE) project=$(project)_hsm ucf=$(ucf)
# Verilog files that always go with builds on this platform.