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-rw-r--r--rtl/alpha_fmc_top.v46
1 files changed, 12 insertions, 34 deletions
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 03c2802..1bc1ce2 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -8,7 +8,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -67,46 +67,25 @@ module alpha_fmc_top
//----------------------------------------------------------------
// Clock Manager
//
- // Clock manager is used to generate SYS_CLK from GCLK
- // and implement the reset logic.
+ // Clock manager is used to buffer FMC_CLK and implement reset logic.
// ----------------------------------------------------------------
- wire sys_clk;
- wire sys_rst_n;
+ wire sys_clk; // system clock (90 MHz)
+ wire sys_rst_n; // active-low reset
- alpha_clkmgr #
- (
- .CLK_OUT_MUL (20.0), // 2..64
- .CLK_OUT_DIV (20.0) // 1..128
- )
- clkmgr
- (
- .gclk (gclk_pin),
-
- .sys_clk (sys_clk),
- .sys_rst_n (sys_rst_n)
- );
-
-
- //----------------------------------------------------------------
- // BUFG
- //
- // FMC clock must be routed through the global clocking backbone.
- // ----------------------------------------------------------------
- wire fmc_clk_bug;
-
- BUFG BUFG_fmc_clk
- (
- .I (fmc_clk),
- .O (fmc_clk_bufg)
- );
+ alpha_clkmgr clkmgr
+ (
+ .fmc_clk (fmc_clk),
+
+ .sys_clk (sys_clk),
+ .sys_rst_n (sys_rst_n)
+ );
//----------------------------------------------------------------
// FMC Arbiter
//
- // FMC arbiter handles FMC access and transfers it into
- // `sys_clk' clock domain.
+ // FMC arbiter handles FMC accesses.
//----------------------------------------------------------------
wire [23: 0] sys_fmc_addr; // address
@@ -121,7 +100,6 @@ module alpha_fmc_top
)
fmc
(
- .fmc_clk(fmc_clk_bufg),
.fmc_a(fmc_a),
.fmc_d(fmc_d),
.fmc_ne1(fmc_ne1),