diff options
| -rw-r--r-- | build/Makefile | 4 | ||||
| -rw-r--r-- | build/xilinx.mk | 1 | ||||
| -rw-r--r-- | build/xilinx.opt | 1 |
3 files changed, 5 insertions, 1 deletions
diff --git a/build/Makefile b/build/Makefile index fc3a45b..0c61dba 100644 --- a/build/Makefile +++ b/build/Makefile @@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh ucf ?= ../ucf/$(project).ucf +# Verilog include directories, if needed + +vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode + all: $(project).bit # Build the default core_selector if it doesn't already exist. diff --git a/build/xilinx.mk b/build/xilinx.mk index abeff7b..76d0110 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -152,6 +152,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-top $(top_module)" >> $@ echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ + echo "-vlgincdir {$(vlgincdir)}" >> $@ cat ./xilinx.opt $(optfile) >> $@ junk += $(project).scr diff --git a/build/xilinx.opt b/build/xilinx.opt index f7ce206..7fe9d8b 100644 --- a/build/xilinx.opt +++ b/build/xilinx.opt @@ -40,4 +40,3 @@ -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 --vlgincdir {../../../lib/lowlevel ../../../math/ecdsalib/rtl/microcode} |