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-rw-r--r--build/Makefile2
-rw-r--r--rtl/alpha_clkmgr.v38
-rw-r--r--rtl/alpha_fmc_top.v64
-rw-r--r--rtl/alpha_regs.v2
-rw-r--r--rtl/clkmgr_mmcm.v31
-rw-r--r--ucf/alpha_fmc.ucf54
6 files changed, 89 insertions, 102 deletions
diff --git a/build/Makefile b/build/Makefile
index 6634de7..2fc9fe0 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -48,8 +48,6 @@ vfiles = \
$(CORE_TREE)/platform/alpha/rtl/alpha_clkmgr.v \
$(CORE_TREE)/platform/alpha/rtl/clkmgr_mmcm.v \
./core_selector.v \
- $(CORE_TREE)/comm/fmc/src/rtl/cdc_bus_pulse.v \
- $(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter_cdc.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_arbiter.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_d_phy.v \
$(CORE_TREE)/comm/fmc/src/rtl/fmc_indicator.v \
diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v
index f870a75..5c4099e 100644
--- a/rtl/alpha_clkmgr.v
+++ b/rtl/alpha_clkmgr.v
@@ -7,7 +7,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -39,19 +39,28 @@
module alpha_clkmgr
(
- input wire gclk, // signal from clock pin
+ input wire fmc_clk, // signal from clock pin
- output wire sys_clk, // buffered system clock output
+ output wire sys_clk, // buffered system clock output
output wire sys_rst_n // system reset output (async set, sync clear, active-low)
);
//
- // Parameters
- //
- parameter CLK_OUT_MUL = 20.0;
- parameter CLK_OUT_DIV = 20.0;
-
+ // Settings
+ //
+
+ /*
+ * fmc_clk is 90 MHz, sys_clk is also 90 MHz routed through an MMCM.
+ *
+ * VCO frequency is 1080 MHz.
+ *
+ */
+ localparam CLK_OUT_MUL = 12.0;
+ localparam CLK_OUT_DIV = 12.0;
+ localparam CLK_OUT_PHI = 45.0;
+
+
//
// Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
//
@@ -63,21 +72,22 @@ module alpha_clkmgr
clkmgr_mmcm #
(
- .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64
- .CLK_OUT_DIV (CLK_OUT_DIV) // 1..128
+ .CLK_OUT_MUL (CLK_OUT_MUL), // 2..64
+ .CLK_OUT_DIV (CLK_OUT_DIV), // 1..128
+ .CLK_OUT_PHI (CLK_OUT_PHI) // 0.0..360.0
)
mmcm
(
- .clk_in (gclk),
+ .gclk_in (fmc_clk),
.reset_in (mmcm_reset),
.gclk_out (gclk_int),
.gclk_missing_out (gclk_missing),
- .clk_out (sys_clk),
+ .clk_out (sys_clk),
.clk_valid_out (mmcm_locked)
);
-
+
//
@@ -93,7 +103,7 @@ module alpha_clkmgr
always @(posedge gclk_int or posedge gclk_missing)
//
- if ((gclk_missing == 1'b1))
+ if (gclk_missing == 1'b1)
mmcm_rst_shreg <= {16{1'b1}};
else
mmcm_rst_shreg <= {mmcm_rst_shreg[14:0], 1'b0};
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 03c2802..a07beee 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -8,7 +8,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -67,46 +67,25 @@ module alpha_fmc_top
//----------------------------------------------------------------
// Clock Manager
//
- // Clock manager is used to generate SYS_CLK from GCLK
- // and implement the reset logic.
+ // Clock manager is used to buffer FMC_CLK and implement reset logic.
// ----------------------------------------------------------------
- wire sys_clk;
- wire sys_rst_n;
+ wire sys_clk; // system clock (90 MHz)
+ wire sys_rst_n; // active-low reset
- alpha_clkmgr #
- (
- .CLK_OUT_MUL (20.0), // 2..64
- .CLK_OUT_DIV (20.0) // 1..128
- )
- clkmgr
- (
- .gclk (gclk_pin),
-
- .sys_clk (sys_clk),
- .sys_rst_n (sys_rst_n)
- );
-
-
- //----------------------------------------------------------------
- // BUFG
- //
- // FMC clock must be routed through the global clocking backbone.
- // ----------------------------------------------------------------
- wire fmc_clk_bug;
-
- BUFG BUFG_fmc_clk
- (
- .I (fmc_clk),
- .O (fmc_clk_bufg)
- );
+ alpha_clkmgr clkmgr
+ (
+ .fmc_clk (fmc_clk),
+
+ .sys_clk (sys_clk),
+ .sys_rst_n (sys_rst_n)
+ );
//----------------------------------------------------------------
// FMC Arbiter
//
- // FMC arbiter handles FMC access and transfers it into
- // `sys_clk' clock domain.
+ // FMC arbiter handles FMC accesses.
//----------------------------------------------------------------
wire [23: 0] sys_fmc_addr; // address
@@ -121,7 +100,6 @@ module alpha_fmc_top
)
fmc
(
- .fmc_clk(fmc_clk_bufg),
.fmc_a(fmc_a),
.fmc_d(fmc_d),
.fmc_ne1(fmc_ne1),
@@ -162,6 +140,20 @@ module alpha_fmc_top
// hashes, RNGs and ciphers to different regions (segments) of memory.
//----------------------------------------------------------------
+ // A note on byte-swapping:
+ // STM32 is little-endian, while the register interface here is
+ // big-endian. The software reads and writes 32-bit integer values,
+ // which means transmitting the least significant byte first. Up to
+ // now, we've been doing byte-swapping in software, which is
+ // inefficient, especially for bulk data transfer. So now we're doing
+ // the byte-swapping in hardware.
+
+ wire [31:0] write_data;
+ assign write_data = {sys_fmc_dout[7:0], sys_fmc_dout[15:8], sys_fmc_dout[23:16], sys_fmc_dout[31:24]};
+
+ wire [31 : 0] read_data;
+ assign sys_fmc_din = {read_data[7:0], read_data[15:8], read_data[23:16], read_data[31:24]};
+
core_selector cores
(
.sys_clk(sys_clk),
@@ -170,8 +162,8 @@ module alpha_fmc_top
.sys_fmc_addr(sys_fmc_addr),
.sys_fmc_wr(sys_fmc_wren),
.sys_fmc_rd(sys_fmc_rden),
- .sys_write_data(sys_fmc_dout),
- .sys_read_data(sys_fmc_din),
+ .sys_write_data(write_data),
+ .sys_read_data(read_data),
.noise(ct_noise),
diff --git a/rtl/alpha_regs.v b/rtl/alpha_regs.v
index a53d2d3..ce17863 100644
--- a/rtl/alpha_regs.v
+++ b/rtl/alpha_regs.v
@@ -68,7 +68,7 @@ module board_regs
// Core ID constants.
localparam CORE_NAME0 = 32'h414c5048; // "ALPH"
localparam CORE_NAME1 = 32'h41202020; // "A "
- localparam CORE_VERSION = 32'h302e3130; // "0.10"
+ localparam CORE_VERSION = 32'h302e3230; // "0.20"
diff --git a/rtl/clkmgr_mmcm.v b/rtl/clkmgr_mmcm.v
index 852288b..03b0747 100644
--- a/rtl/clkmgr_mmcm.v
+++ b/rtl/clkmgr_mmcm.v
@@ -6,7 +6,7 @@
//
//
// Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
@@ -38,22 +38,23 @@
module clkmgr_mmcm
(
- input wire clk_in,
+ input wire gclk_in,
input wire reset_in,
output wire gclk_out,
output wire gclk_missing_out,
- output wire clk_out,
+ output wire clk_out,
output wire clk_valid_out
);
- //
- // Parameters
- //
- parameter CLK_OUT_MUL = 20.0; // multiply factor for output clock frequency (2..64)
- parameter CLK_OUT_DIV = 20.0; // divide factor for output clock frequency (1..128)
+ //
+ // Parameters
+ //
+ parameter CLK_OUT_MUL = 12.0; // multiply factor for output clock frequency (2..64)
+ parameter CLK_OUT_DIV = 12.0; // divide factor for output clock frequency (1..128)
+ parameter CLK_OUT_PHI = 45.0; // clock phase shift (0.0..360.0)
//
@@ -61,12 +62,12 @@ module clkmgr_mmcm
//
(* BUFFER_TYPE="NONE" *)
- wire clk_in_ibufg;
+ wire gclk_in_ibufg;
IBUFG IBUFG_gclk
(
- .I (clk_in),
- .O (clk_in_ibufg)
+ .I (gclk_in),
+ .O (gclk_in_ibufg)
);
@@ -80,7 +81,7 @@ module clkmgr_mmcm
MMCME2_ADV #
(
- .CLKIN1_PERIOD (20.000),
+ .CLKIN1_PERIOD (11.111),
.REF_JITTER1 (0.010),
.STARTUP_WAIT ("FALSE"),
@@ -94,7 +95,7 @@ module clkmgr_mmcm
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLK_OUT_DIV),
- .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_PHASE (CLK_OUT_PHI),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT0_DUTY_CYCLE (0.500),
@@ -102,7 +103,7 @@ module clkmgr_mmcm
)
MMCME2_ADV_inst
(
- .CLKIN1 (clk_in_ibufg),
+ .CLKIN1 (gclk_in_ibufg),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
@@ -151,7 +152,7 @@ module clkmgr_mmcm
//
// Mapping
//
- assign gclk_out = clk_in_ibufg;
+ assign gclk_out = gclk_in_ibufg;
assign clk_valid_out = mmcm_locked;
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index 5e71c64..7926762 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -7,7 +7,7 @@
#
#
# Author: Pavel Shatov
-# Copyright (c) 2016, NORDUnet A/S All rights reserved.
+# Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -39,23 +39,28 @@
#--------------------------------------------------------------------------------
-# GCLK Timing (fixed at 50 MHz)
+# GCLK Timing (fixed at 50 MHz) - NOT USED
#--------------------------------------------------------------------------------
-NET "gclk_pin" TNM_NET = TNM_gclk;
-TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
+#NET "gclk_pin" TNM_NET = TNM_gclk;
+#TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
#-------------------------------------------------------------------------------
# FMC_CLK Timing (can be up to 90 MHz)
#-------------------------------------------------------------------------------
NET "fmc_clk" TNM_NET = TNM_fmc_clk;
-TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
+
+# 90 MHz
+#TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%;
+
+# 60 MHz
+TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 16.667 ns HIGH 50%;
#-------------------------------------------------------------------------------
# FPGA Pinout
#-------------------------------------------------------------------------------
-#
+#
NET "led_pins<0>" LOC = "U3";
NET "led_pins<1>" LOC = "T1";
NET "led_pins<2>" LOC = "W22";
@@ -145,8 +150,9 @@ NET "mkm_do" LOC = "Y1" | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
# FMC Input Timing
#-------------------------------------------------------------------------------
#
-# The following timing values were derived from pages 173-175 of the STM32F429
-# datasheet. Control signals NE1, NL and NWE all have different timing values.
+# The following timing values were derived from Figures 61-62 and Tables 96-97
+# (pages 180-182) of the STM32F429 datasheet ("DocID024030 Rev 10").
+# Control signals NE1, NL and NWE all have different timing values.
# Instead of writing individual constraints for every control signal, the most
# strict constraint is applied to all control signals. This should not cause
# any P&R issues, since Spartan-6 (and Artix-7) can handle 90 MHz easily.
@@ -154,10 +160,9 @@ NET "mkm_do" LOC = "Y1" | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
# NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
#
# Data and Address buses also have different timings, with Data bus timing being
-# more strict. The same approach is used here, i.e. timing for Data bus is
-# applied to Address bus too.
+# more strict.
#
-# Oh, and stupid datasheet doesn't explicitly specify hold time for the data bus!
+# Oh, and the datasheet doesn't explicitly specify hold time for the data bus.
#
NET "fmc_d<*>" TNM = "TNM_FMC_IN_DATA" ;
@@ -167,37 +172,18 @@ NET "fmc_ne1" TNM = "TNM_FMC_IN_CONTROL" ;
NET "fmc_nl" TNM = "TNM_FMC_IN_CONTROL" ;
NET "fmc_nwe" TNM = "TNM_FMC_IN_CONTROL" ;
-TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
-TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 3.0 ns VALID 8.5 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 5.5 ns VALID 5.5 ns BEFORE "fmc_clk" RISING ;
TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk" RISING ;
+
#-------------------------------------------------------------------------------
# FMC Output Timing
#-------------------------------------------------------------------------------
-#
-# NWAIT signal is not constrained, since it is polled by STM32.
-#
-
NET "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
-TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 16.7 ns AFTER "fmc_clk" FALLING;
-
+TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 6.0 ns AFTER "fmc_clk" RISING;
-#-------------------------------------------------------------------------------
-# CDC Paths
-#-------------------------------------------------------------------------------
-INST "fmc/fmc_cdc/cdc_fmc_sys/src_ff" TNM = "TNM_from_fmc_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/src_latch*" TNM = "TNM_from_fmc_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/ff_sync*" TNM = "TNM_to_sys_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/dst_latch*" TNM = "TNM_to_sys_clk";
-
-INST "fmc/fmc_cdc/cdc_sys_fmc/src_ff" TNM = "TNM_from_sys_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/src_latch*" TNM = "TNM_from_sys_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/ff_sync*" TNM = "TNM_to_fmc_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/dst_latch*" TNM = "TNM_to_fmc_clk";
-
-TIMESPEC "TS_fmc_clk_2_sys_clk" = FROM "TNM_from_fmc_clk" TO "TNM_to_sys_clk" TIG;
-TIMESPEC "TS_sys_clk_2_fmc_clk" = FROM "TNM_from_sys_clk" TO "TNM_to_fmc_clk" TIG;
#======================================================================
# EOF alpha_fmc.ucf
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 12:23:24 +0000