diff options
| -rw-r--r-- | build/Makefile | 4 | ||||
| -rw-r--r-- | rtl/alpha_fmc_top.v | 84 | ||||
| -rw-r--r-- | ucf/alpha_fmc.ucf | 5 |
3 files changed, 56 insertions, 37 deletions
diff --git a/build/Makefile b/build/Makefile index ea8d032..aed01df 100644 --- a/build/Makefile +++ b/build/Makefile @@ -44,6 +44,10 @@ rsa: $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s rsa $(MAKE) project=$(project)_rsa ucf=$(ucf) +mkmif: + $(CONFIG)/config.py -c $(CONFIG)/config.cfg -s mkmif + $(MAKE) project=$(project)_mkmif ucf=$(ucf) + # Verilog files that always go with builds on this platform. vfiles = \ diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v index e829545..6410d44 100644 --- a/rtl/alpha_fmc_top.v +++ b/rtl/alpha_fmc_top.v @@ -42,18 +42,23 @@ module alpha_fmc_top ( - input wire gclk_pin, // 50 MHz + input wire gclk_pin, // 50 MHz - input wire ct_noise, // cryptech avalanche noise circuit + input wire ct_noise, // cryptech avalanche noise circuit - input wire fmc_clk, // clock - input wire [23: 0] fmc_a, // address - inout wire [31: 0] fmc_d, // data - input wire fmc_ne1, // chip select - input wire fmc_noe, // output enable - input wire fmc_nwe, // write enable - input wire fmc_nl, // latch enable - output wire fmc_nwait,// wait + input wire fmc_clk, // clock + input wire [23: 0] fmc_a, // address + inout wire [31: 0] fmc_d, // data + input wire fmc_ne1, // chip select + input wire fmc_noe, // output enable + input wire fmc_nwe, // write enable + input wire fmc_nl, // latch enable + output wire fmc_nwait,// wait + + output wire mkm_sclk, + output wire mkm_cs_n, + input wire mkm_do, + output wire mkm_di, output wire [3: 0] led_pins // {red, yellow, green, blue} ); @@ -75,8 +80,8 @@ module alpha_fmc_top ) clkmgr ( - .gclk (gclk_pin),
- + .gclk (gclk_pin), + .sys_clk (sys_clk), .sys_rst_n (sys_rst_n) ); @@ -103,14 +108,14 @@ module alpha_fmc_top // FMC arbiter handles FMC access and transfers it into // `sys_clk' clock domain. //---------------------------------------------------------------- -`define test
+ //`define test wire [23: 0] sys_fmc_addr; // address wire sys_fmc_wren; // write enable wire sys_fmc_rden; // read enable wire [31: 0] sys_fmc_dout; // data output (from STM32 to FPGA) `ifdef test - reg [31: 0] sys_fmc_din; // data input (from FPGA to STM32) + reg [31: 0] sys_fmc_din; // data input (from FPGA to STM32) `else wire [31: 0] sys_fmc_din; // data input (from FPGA to STM32) `endif @@ -180,20 +185,20 @@ module alpha_fmc_top // //---------------------------------------------------------------- reg [31: 0] test_reg; -
-
-
- //
- // Noise Capture Register
- //
- reg [31: 0] noise_reg;
-
- always @(posedge sys_clk)
- //
- noise_reg <= {noise_reg[30:0], ct_noise};
-
-
- + + + + // + // Noise Capture Register + // + reg [31: 0] noise_reg; + + always @(posedge sys_clk) + // + noise_reg <= {noise_reg[30:0], ct_noise}; + + + always @(posedge sys_clk) // if (sys_fmc_wren) begin @@ -236,16 +241,21 @@ module alpha_fmc_top .sys_write_data(sys_fmc_dout), .sys_read_data(sys_fmc_din), - .noise(ct_noise) + .noise(ct_noise), + + .mkm_sclk(mkm_sclk), + .mkm_cs_n(mkm_cs_n), + .mkm_do(mkm_do), + .mkm_di(mkm_di) ); -`endif
-
-
- //
- // Dummy assignment to bypass unconnected outpins pins check in BitGen
- //
-
- assign led_pins[3:1] = 3'b000; +`endif + + + // + // Dummy assignment to bypass unconnected outpins pins check in BitGen + // + + assign led_pins[3:1] = 3'b000; endmodule diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf index 34b2072..39a2c31 100644 --- a/ucf/alpha_fmc.ucf +++ b/ucf/alpha_fmc.ucf @@ -136,6 +136,11 @@ NET "fmc_d<31>" LOC = "P21" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | NET "ct_noise" LOC = "W19" | IOSTANDARD = "LVCMOS33" ; +NET "mkm_sclk" LOC = "V3" | IOSTANDARD = "LVCMOS33" ; +NET "mkm_cs_n" LOC = "W2" | IOSTANDARD = "LVCMOS33" ; +NET "mkm_do" LOC = "W1" | IOSTANDARD = "LVCMOS33" ; +NET "mkm_di" LOC = "Y1" | IOSTANDARD = "LVCMOS33" ; + #------------------------------------------------------------------------------- # FMC Input Timing #------------------------------------------------------------------------------- |