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-rw-r--r--build/Makefile34
1 files changed, 3 insertions, 31 deletions
diff --git a/build/Makefile b/build/Makefile
index 8115637..4328fbd 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -32,37 +32,9 @@ core_selector.v core_vfiles.mk:
# Build some different configurations
-bare:
- $(CONFIG_GEN) -p bare
- $(MAKE) project=$(project)_bare ucf=$(ucf)
-
-trng:
- $(CONFIG_GEN) -p trng
- $(MAKE) project=$(project)_trng ucf=$(ucf)
-
-hash:
- $(CONFIG_GEN) -p hash
- $(MAKE) project=$(project)_hash ucf=$(ucf)
-
-rsa:
- $(CONFIG_GEN) -p rsa
- $(MAKE) project=$(project)_rsa ucf=$(ucf)
-
-mkmif:
- $(CONFIG_GEN) -p mkmif
- $(MAKE) project=$(project)_mkmif ucf=$(ucf)
-
-hsm:
- $(CONFIG_GEN) -p hsm
- $(MAKE) project=$(project)_hsm ucf=$(ucf)
-
-hsm-super:
- $(CONFIG_GEN) -p hsm-super
- $(MAKE) project=$(project)_hsm-super ucf=$(ucf)
-
-keywrap:
- $(CONFIG_GEN) -p keywrap
- $(MAKE) project=$(project)_keywrap ucf=$(ucf)
+bare trng hash mkmif rsa hsm hsm-super keywrap:
+ $(CONFIG_GEN) -p $@
+ $(MAKE) project=$(project)_$@ ucf=$(ucf)
# Verilog files that always go with builds on this platform.