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-rw-r--r--build/Makefile4
-rw-r--r--build/xilinx.mk1
2 files changed, 5 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile
index 4328fbd..6634de7 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
+# Verilog include directories, if needed
+
+vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
all: $(project).bit
# Build the default core_selector if it doesn't already exist.
diff --git a/build/xilinx.mk b/build/xilinx.mk
index abeff7b..76d0110 100644
--- a/build/xilinx.mk
+++ b/build/xilinx.mk
@@ -152,6 +152,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt
echo "-top $(top_module)" >> $@
echo "-ifn $(project).prj" >> $@
echo "-ofn $(project).ngc" >> $@
+ echo "-vlgincdir {$(vlgincdir)}" >> $@
cat ./xilinx.opt $(optfile) >> $@
junk += $(project).scr