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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2021-10-26 16:50:06 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2021-10-26 16:50:06 +0300
commitd42f31d0b05361052529d42fc853bc8bdf254bbb (patch)
tree1d1e1e193db0cf14b89e85efa8a4b9ac748d09fe /xdc
parent0fb070a2a709f15f76c80b532b30550eaea73240 (diff)
XDC equivalent of UCF timing constraints for ISE.
Note, that Vivado needs an extra constraint to bypass combinatorial loop DRC check, otherwise bitstream generation will fail.
Diffstat (limited to 'xdc')
-rw-r--r--xdc/alpha_fmc_timing.xdc17
1 files changed, 16 insertions, 1 deletions
diff --git a/xdc/alpha_fmc_timing.xdc b/xdc/alpha_fmc_timing.xdc
index e311270..218a573 100644
--- a/xdc/alpha_fmc_timing.xdc
+++ b/xdc/alpha_fmc_timing.xdc
@@ -1 +1,16 @@
-create_clock -period 22.222 -name clk_fmc -waveform {0.000 11.111} [get_ports clk_fmc]
+set_input_delay -clock [get_clocks clk_fmc] -min 10.0 [get_ports {fmc_d[*]}]
+set_input_delay -clock [get_clocks clk_fmc] -max 14.8 [get_ports {fmc_d[*]}]
+
+set_input_delay -clock [get_clocks clk_fmc] -min -1.0 [get_ports {fmc_a[*]}]
+set_input_delay -clock [get_clocks clk_fmc] -max 12.3 [get_ports {fmc_a[*]}]
+
+set_input_delay -clock [get_clocks clk_fmc] -min 4.0 [get_ports {fmc_ne1 fmc_nl fmc_nwe}]
+set_input_delay -clock [get_clocks clk_fmc] -max 12.8 [get_ports {fmc_ne1 fmc_nl fmc_nwe}]
+
+set_multicycle_path -from [get_cells {cores/reg_read_data_*[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -setup 2
+set_multicycle_path -from [get_cells {cores/addr_core_num_dly2_reg[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -setup 2
+
+set_multicycle_path -from [get_cells {cores/reg_read_data_*[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -hold 1
+set_multicycle_path -from [get_cells {cores/addr_core_num_dly2_reg[*]}] -to [get_cells {cores/pipe_read_data_*[*]}] -hold 1
+
+set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets cores/trng_inst/entropy2/core/oscillators[0].rosc_array/dout_new]