Initial commit, based on core/platform/novena[/fmc], probably doesn't work, but gives Pavel and Fredrik a place to put their stuff.

1 files changed, 198 insertions, 0 deletions

diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
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+#======================================================================
+#
+# alpha_fmc.ucf
+# -------------------
+# Constraint file for implementing the Cryptech Alpha base
+# for the Xilinx Spartan6 LX45 on the Alpha.
+#
+#
+# Author: Pavel Shatov
+# Copyright (c) 2014, NORDUnet A/S All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# - Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+#
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+#
+# - Neither the name of the NORDUnet nor the names of its contributors may
+#   be used to endorse or promote products derived from this software
+#   without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#======================================================================
+
+#-------------------------------------------------------------------------------
+CONFIG  VCCAUX = 3.3;
+#-------------------------------------------------------------------------------
+
+
+#--------------------------------------------------------------------------------
+# GCLK Timing (fixed at 50 MHz)
+#--------------------------------------------------------------------------------
+NET  "gclk_p_pin" TNM_NET = TNM_gclk;
+TIMESPEC  TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
+
+
+#-------------------------------------------------------------------------------
+# FMC_CLK Timing (can be up to 90 MHz)
+#-------------------------------------------------------------------------------
+NET  "fmc_clk" TNM_NET = TNM_fmc_clk;
+TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
+
+
+#-------------------------------------------------------------------------------
+# FPGA Pinout
+#-------------------------------------------------------------------------------
+NET  "led_pin"         LOC = "A16" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+NET  "apoptosis_pin"   LOC = "K1"  | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+NET  "reset_mcu_b_pin" LOC = "F1"  | IOSTANDARD = "LVCMOS33" | PULLUP;
+#
+NET  "gclk_p_pin"      LOC = "H2"  | IOSTANDARD = "LVDS_25"  | DIFF_TERM = "TRUE";
+NET  "gclk_n_pin"      LOC = "H1"  | IOSTANDARD = "LVDS_25"  | DIFF_TERM = "TRUE";
+#
+NET  "fmc_clk"         LOC = "T8"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_ne1"         LOC = "R7"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_noe"         LOC = "R8"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_nwe"         LOC = "V11" | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_nl"          LOC = "T7"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_nwait"       LOC = "V8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+#
+NET  "fmc_a<0>"        LOC = "V7"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<1>"        LOC = "M5"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<2>"        LOC = "L4"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<3>"        LOC = "M3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<4>"        LOC = "L3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<5>"        LOC = "P2"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<6>"        LOC = "K3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<7>"        LOC = "K4"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<8>"        LOC = "R3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<9>"        LOC = "T3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<10>"       LOC = "V4"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<11>"       LOC = "T4"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<12>"       LOC = "J3"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<13>"       LOC = "J1"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<14>"       LOC = "J6"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<15>"       LOC = "U16" | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<16>"       LOC = "M1"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<17>"       LOC = "F2"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<18>"       LOC = "R11" | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<19>"       LOC = "V5"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<20>"       LOC = "G1"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fmc_a<21>"       LOC = "T2"  | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<22>"       LOC = "  "  | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<23>"       LOC = "  "  | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<24>"       LOC = "  "  | IOSTANDARD = "LVCMOS33" ;
+#NET "fmc_a<25>"       LOC = "  "  | IOSTANDARD = "LVCMOS33" ;
+#
+NET  "fmc_d<0>"        LOC = "K2"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<1>"        LOC = "V16" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<2>"        LOC = "V9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<3>"        LOC = "T9"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<4>"        LOC = "T5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<5>"        LOC = "R5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<6>"        LOC = "T10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<7>"        LOC = "R10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<8>"        LOC = "P6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<9>"        LOC = "N5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<10>"       LOC = "V10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<11>"       LOC = "U10" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<12>"       LOC = "L5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<13>"       LOC = "K6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<14>"       LOC = "H4"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<15>"       LOC = "H3"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<16>"       LOC = "K5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<17>"       LOC = "L2"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<18>"       LOC = "L1"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<19>"       LOC = "L7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<20>"       LOC = "T11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<21>"       LOC = "T14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<22>"       LOC = "V14" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<23>"       LOC = "L6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<24>"       LOC = "U13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<25>"       LOC = "V13" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<26>"       LOC = "U11" | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<27>"       LOC = "U8"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<28>"       LOC = "V6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<29>"       LOC = "T6"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<30>"       LOC = "U5"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+NET  "fmc_d<31>"       LOC = "U7"  | IOSTANDARD = "LVCMOS33" | SLEW = "FAST" | DRIVE = 8;
+
+NET  "ct_noise"        LOC = "H7"  | IOSTANDARD = "LVCMOS33" ;
+
+#-------------------------------------------------------------------------------
+# FMC Input Timing
+#-------------------------------------------------------------------------------
+#
+# The following timing values were derived from pages 173-175 of the STM32F429
+# datasheet. Control signals NE1, NL and NWE all have different timing values.
+# Instead of writing individual constraints for every control signal, the most
+# strict constraint is applied to all control signals. This should not cause
+# any P&R issues, since Spartan-6 can handle 90 MHz easily.
+#
+# NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
+#
+# Data and Address buses also have different timings, with Data bus timing being
+# more strict. The same approach is used here, i.e. timing for Data bus is
+# applied to Address bus too.
+#
+# Oh, and stupid datasheet doesn't explicitly specify hold time for the data bus!
+#
+
+NET  "fmc_d<*>" TNM = "TNM_FMC_IN_DATA" ;
+NET  "fmc_a<*>" TNM = "TNM_FMC_IN_ADDR" ;
+
+NET  "fmc_ne1"  TNM = "TNM_FMC_IN_CONTROL" ;
+NET  "fmc_nl"   TNM = "TNM_FMC_IN_CONTROL" ;
+NET  "fmc_nwe"  TNM = "TNM_FMC_IN_CONTROL" ;
+
+TIMEGRP  "TNM_FMC_IN_DATA"    OFFSET = IN 3.0 ns VALID  6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP  "TNM_FMC_IN_ADDR"    OFFSET = IN 3.0 ns VALID  6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP  "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk" RISING ;
+
+#-------------------------------------------------------------------------------
+# FMC Output Timing
+#-------------------------------------------------------------------------------
+#
+# NWAIT signal is not constrained, since it is polled by STM32.
+#
+
+NET  "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
+
+TIMEGRP  "TNM_FMC_OUT_DATA" OFFSET = OUT 11.5 ns AFTER "fmc_clk" FALLING;
+
+
+#-------------------------------------------------------------------------------
+# CDC Paths
+#-------------------------------------------------------------------------------
+INST  "fmc/fmc_cdc/cdc_fmc_sys/src_ff"     TNM = "TNM_from_fmc_clk";
+INST  "fmc/fmc_cdc/cdc_fmc_sys/src_latch*" TNM = "TNM_from_fmc_clk";
+INST  "fmc/fmc_cdc/cdc_fmc_sys/ff_sync*"   TNM = "TNM_to_sys_clk";
+INST  "fmc/fmc_cdc/cdc_fmc_sys/dst_latch*" TNM = "TNM_to_sys_clk";
+
+INST  "fmc/fmc_cdc/cdc_sys_fmc/src_ff"     TNM = "TNM_from_sys_clk";
+INST  "fmc/fmc_cdc/cdc_sys_fmc/src_latch*" TNM = "TNM_from_sys_clk";
+INST  "fmc/fmc_cdc/cdc_sys_fmc/ff_sync*"   TNM = "TNM_to_fmc_clk";
+INST  "fmc/fmc_cdc/cdc_sys_fmc/dst_latch*" TNM = "TNM_to_fmc_clk";
+
+TIMESPEC  "TS_fmc_clk_2_sys_clk" = FROM "TNM_from_fmc_clk" TO "TNM_to_sys_clk" TIG;
+TIMESPEC  "TS_sys_clk_2_fmc_clk" = FROM "TNM_from_sys_clk" TO "TNM_to_fmc_clk" TIG;
+
+#======================================================================
+# EOF alpha_fmc.ucf
+#======================================================================