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authorPaul Selkirk <paul@psgd.org>2019-04-03 17:26:29 -0400
committerPaul Selkirk <paul@psgd.org>2019-04-03 17:26:51 -0400
commit6439bac28538138cb2c49691d5485dd16ab6fa96 (patch)
treef85a7b63b2491c3e5e613faedf289ca4cbd7acaf /ucf/alpha_fmc.ucf
parent1526cfd1166500fa7df689237cfcf950ecc56d4b (diff)
parent516b2975958b05c72f573c37c075e5793c514101 (diff)
Merge branch 'fmc_clk_60mhz' to 'master'
Diffstat (limited to 'ucf/alpha_fmc.ucf')
-rw-r--r--ucf/alpha_fmc.ucf54
1 files changed, 20 insertions, 34 deletions
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index 5e71c64..7926762 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -7,7 +7,7 @@
#
#
# Author: Pavel Shatov
-# Copyright (c) 2016, NORDUnet A/S All rights reserved.
+# Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -39,23 +39,28 @@
#--------------------------------------------------------------------------------
-# GCLK Timing (fixed at 50 MHz)
+# GCLK Timing (fixed at 50 MHz) - NOT USED
#--------------------------------------------------------------------------------
-NET "gclk_pin" TNM_NET = TNM_gclk;
-TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
+#NET "gclk_pin" TNM_NET = TNM_gclk;
+#TIMESPEC TS_gclk = PERIOD TNM_gclk 20 ns HIGH 50%;
#-------------------------------------------------------------------------------
# FMC_CLK Timing (can be up to 90 MHz)
#-------------------------------------------------------------------------------
NET "fmc_clk" TNM_NET = TNM_fmc_clk;
-TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
+
+# 90 MHz
+#TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%;
+
+# 60 MHz
+TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 16.667 ns HIGH 50%;
#-------------------------------------------------------------------------------
# FPGA Pinout
#-------------------------------------------------------------------------------
-#
+#
NET "led_pins<0>" LOC = "U3";
NET "led_pins<1>" LOC = "T1";
NET "led_pins<2>" LOC = "W22";
@@ -145,8 +150,9 @@ NET "mkm_do" LOC = "Y1" | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
# FMC Input Timing
#-------------------------------------------------------------------------------
#
-# The following timing values were derived from pages 173-175 of the STM32F429
-# datasheet. Control signals NE1, NL and NWE all have different timing values.
+# The following timing values were derived from Figures 61-62 and Tables 96-97
+# (pages 180-182) of the STM32F429 datasheet ("DocID024030 Rev 10").
+# Control signals NE1, NL and NWE all have different timing values.
# Instead of writing individual constraints for every control signal, the most
# strict constraint is applied to all control signals. This should not cause
# any P&R issues, since Spartan-6 (and Artix-7) can handle 90 MHz easily.
@@ -154,10 +160,9 @@ NET "mkm_do" LOC = "Y1" | IOSTANDARD = "LVCMOS33" ; # MKM_FPGA_MISO
# NOE signal is not constrained, since it drives "T" input of IOBUF primitive.
#
# Data and Address buses also have different timings, with Data bus timing being
-# more strict. The same approach is used here, i.e. timing for Data bus is
-# applied to Address bus too.
+# more strict.
#
-# Oh, and stupid datasheet doesn't explicitly specify hold time for the data bus!
+# Oh, and the datasheet doesn't explicitly specify hold time for the data bus.
#
NET "fmc_d<*>" TNM = "TNM_FMC_IN_DATA" ;
@@ -167,37 +172,18 @@ NET "fmc_ne1" TNM = "TNM_FMC_IN_CONTROL" ;
NET "fmc_nl" TNM = "TNM_FMC_IN_CONTROL" ;
NET "fmc_nwe" TNM = "TNM_FMC_IN_CONTROL" ;
-TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
-TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 3.0 ns VALID 6.0 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_DATA" OFFSET = IN 3.0 ns VALID 8.5 ns BEFORE "fmc_clk" RISING ;
+TIMEGRP "TNM_FMC_IN_ADDR" OFFSET = IN 5.5 ns VALID 5.5 ns BEFORE "fmc_clk" RISING ;
TIMEGRP "TNM_FMC_IN_CONTROL" OFFSET = IN 5.0 ns VALID 10.0 ns BEFORE "fmc_clk" RISING ;
+
#-------------------------------------------------------------------------------
# FMC Output Timing
#-------------------------------------------------------------------------------
-#
-# NWAIT signal is not constrained, since it is polled by STM32.
-#
-
NET "fmc_d<*>" TNM = "TNM_FMC_OUT_DATA" ;
-TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 16.7 ns AFTER "fmc_clk" FALLING;
-
+TIMEGRP "TNM_FMC_OUT_DATA" OFFSET = OUT 6.0 ns AFTER "fmc_clk" RISING;
-#-------------------------------------------------------------------------------
-# CDC Paths
-#-------------------------------------------------------------------------------
-INST "fmc/fmc_cdc/cdc_fmc_sys/src_ff" TNM = "TNM_from_fmc_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/src_latch*" TNM = "TNM_from_fmc_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/ff_sync*" TNM = "TNM_to_sys_clk";
-INST "fmc/fmc_cdc/cdc_fmc_sys/dst_latch*" TNM = "TNM_to_sys_clk";
-
-INST "fmc/fmc_cdc/cdc_sys_fmc/src_ff" TNM = "TNM_from_sys_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/src_latch*" TNM = "TNM_from_sys_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/ff_sync*" TNM = "TNM_to_fmc_clk";
-INST "fmc/fmc_cdc/cdc_sys_fmc/dst_latch*" TNM = "TNM_to_fmc_clk";
-
-TIMESPEC "TS_fmc_clk_2_sys_clk" = FROM "TNM_from_fmc_clk" TO "TNM_to_sys_clk" TIG;
-TIMESPEC "TS_sys_clk_2_fmc_clk" = FROM "TNM_from_sys_clk" TO "TNM_to_fmc_clk" TIG;
#======================================================================
# EOF alpha_fmc.ucf