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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-21 15:43:40 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-01-21 15:43:40 +0300
commit7bf84ba5628678abc9d9ffa58c639eca7f3e095b (patch)
treee984a0eaaa15228992d073837f2b1328baf21b80 /rtl
parent923e7d3b3cf7dd065c87fb33cab1f130bbf56206 (diff)
Testbench for the new clock manager.
Diffstat (limited to 'rtl')
-rw-r--r--rtl/bench/tb_clkmgr.v38
1 files changed, 38 insertions, 0 deletions
diff --git a/rtl/bench/tb_clkmgr.v b/rtl/bench/tb_clkmgr.v
new file mode 100644
index 0000000..a987e1c
--- /dev/null
+++ b/rtl/bench/tb_clkmgr.v
@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+
+module tb_clkmgr;
+
+ // Input
+ reg fmc_clk = 1'b0;
+
+ // Clock
+ always #11.111 fmc_clk = ~fmc_clk;
+
+ // Outputs
+ wire io_clk;
+ wire sys_clk;
+ wire sys_rst_n;
+ wire core_clk;
+
+ // Internals
+ reg fmc_clk_inhibit = 1'b0;
+
+ // UUT
+ alpha_clkmgr uut
+ (
+ .fmc_clk(fmc_clk & ~fmc_clk_inhibit),
+ .io_clk(io_clk),
+ .sys_clk(sys_clk),
+ .sys_rst_n(sys_rst_n),
+ .core_clk(core_clk)
+ );
+
+ // Script
+ initial begin
+ #399000;
+ fmc_clk_inhibit = 1'b1;
+ #1000;
+ fmc_clk_inhibit = 1'b0;
+ end
+
+endmodule