Merge branch 'fmc_clk_60mhz' to 'master'

3 files changed, 52 insertions, 63 deletions

diff --git a/rtl/alpha_clkmgr.v b/rtl/alpha_clkmgr.v
index f870a75..5c4099e 100644
--- a/rtl/alpha_clkmgr.v
+++ b/rtl/alpha_clkmgr.v
@@ -7,7 +7,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -39,19 +39,28 @@
 
 module alpha_clkmgr
   (
-   input wire  gclk,            // signal from clock pin
+   input wire  fmc_clk,         // signal from clock pin
 
-   output wire sys_clk,         // buffered system clock output
+   output wire sys_clk,         // buffered system clock output

    output wire sys_rst_n        // system reset output (async set, sync clear, active-low)
    );
 
 
    //
-   // Parameters
-   //
-   parameter    CLK_OUT_MUL     = 20.0;
-   parameter    CLK_OUT_DIV     = 20.0;
-
+   // Settings
+   //

+	

+	/*

+	 * fmc_clk is 90 MHz, sys_clk is also 90 MHz routed through an MMCM.

+	 *

+	 * VCO frequency is 1080 MHz.

+	 *

+	 */
+   localparam CLK_OUT_MUL   = 12.0;
+   localparam CLK_OUT_DIV   = 12.0;

+   localparam CLK_OUT_PHI   = 45.0;

+

+

    //
    // Wrapper for Xilinx-specific MMCM (Mixed Mode Clock Manager) primitive.
    //
@@ -63,21 +72,22 @@ module alpha_clkmgr
 
    clkmgr_mmcm #
      (
-			.CLK_OUT_MUL              (CLK_OUT_MUL),	// 2..64
-			.CLK_OUT_DIV              (CLK_OUT_DIV)	// 1..128
+			.CLK_OUT_MUL (CLK_OUT_MUL),	// 2..64
+			.CLK_OUT_DIV (CLK_OUT_DIV),	// 1..128

+			.CLK_OUT_PHI (CLK_OUT_PHI)	// 0.0..360.0

       )
    mmcm
      (
-      .clk_in                   (gclk),
+      .gclk_in                  (fmc_clk),
       .reset_in                 (mmcm_reset),
 
       .gclk_out                 (gclk_int),
       .gclk_missing_out         (gclk_missing),
 
-      .clk_out                  (sys_clk),
+      .clk_out                  (sys_clk),

       .clk_valid_out            (mmcm_locked)
       );

-		
+      		
 
 
    //
@@ -93,7 +103,7 @@ module alpha_clkmgr
 
    always @(posedge gclk_int or posedge gclk_missing)
      //
-     if ((gclk_missing == 1'b1))
+     if (gclk_missing == 1'b1)
        mmcm_rst_shreg    <= {16{1'b1}};
      else
        mmcm_rst_shreg    <= {mmcm_rst_shreg[14:0], 1'b0};
diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 03c2802..1bc1ce2 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -8,7 +8,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018 NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -67,46 +67,25 @@ module alpha_fmc_top
    //----------------------------------------------------------------
    // Clock Manager
    //
-   // Clock manager is used to generate SYS_CLK from GCLK
-   // and implement the reset logic.
+   // Clock manager is used to buffer FMC_CLK and implement reset logic.
    // ----------------------------------------------------------------
-   wire               sys_clk;
-   wire               sys_rst_n;
+   wire               sys_clk;		// system clock (90 MHz)
+   wire               sys_rst_n;	// active-low reset
 
-   alpha_clkmgr #
-     (
-      .CLK_OUT_MUL      (20.0),    // 2..64
-      .CLK_OUT_DIV      (20.0)     // 1..128
-      )
-   clkmgr
-     (
-      .gclk      (gclk_pin),
-      
-      .sys_clk   (sys_clk),
-      .sys_rst_n (sys_rst_n)
-      );
-
-
-   //----------------------------------------------------------------
-   // BUFG
-   //
-   // FMC clock must be routed through the global clocking backbone.
-   // ----------------------------------------------------------------
-   wire               fmc_clk_bug;
-
-   BUFG BUFG_fmc_clk
-     (
-      .I                (fmc_clk),
-      .O                (fmc_clk_bufg)
-      );
+	alpha_clkmgr clkmgr
+	(
+		.fmc_clk		(fmc_clk),
+	
+		.sys_clk		(sys_clk),
+		.sys_rst_n		(sys_rst_n)
+	);
 
 
 
    //----------------------------------------------------------------
    // FMC Arbiter
    //
-   // FMC arbiter handles FMC access and transfers it into
-   // `sys_clk' clock domain.
+   // FMC arbiter handles FMC accesses.
    //----------------------------------------------------------------
 
    wire [23: 0]       sys_fmc_addr;     // address
@@ -121,7 +100,6 @@ module alpha_fmc_top
       )
    fmc
      (
-      .fmc_clk(fmc_clk_bufg),
       .fmc_a(fmc_a),
       .fmc_d(fmc_d),
       .fmc_ne1(fmc_ne1),
diff --git a/rtl/clkmgr_mmcm.v b/rtl/clkmgr_mmcm.v
index 852288b..03b0747 100644
--- a/rtl/clkmgr_mmcm.v
+++ b/rtl/clkmgr_mmcm.v
@@ -6,7 +6,7 @@
 //
 //
 // Author: Pavel Shatov
-// Copyright (c) 2016, NORDUnet A/S All rights reserved.
+// Copyright (c) 2016, 2018, NORDUnet A/S All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
@@ -38,22 +38,23 @@
 
 module clkmgr_mmcm
   (
-   input wire  clk_in,
+   input wire  gclk_in,
    input wire  reset_in,
   
    output wire gclk_out,
    output wire gclk_missing_out,
 
-   output wire clk_out,
+   output wire clk_out,

    output wire clk_valid_out
    );
    
    
-   //
-   // Parameters
-   //
-   parameter    CLK_OUT_MUL     = 20.0;    // multiply factor for output clock frequency (2..64)
-   parameter    CLK_OUT_DIV     = 20.0;    // divide factor for output clock frequency (1..128)
+    //
+    // Parameters
+    //
+    parameter    CLK_OUT_MUL     = 12.0;    // multiply factor for output clock frequency (2..64)
+    parameter    CLK_OUT_DIV     = 12.0;    // divide factor for output clock frequency (1..128)

+    parameter	 CLK_OUT_PHI	 = 45.0;    // clock phase shift (0.0..360.0)

    
    
    //
@@ -61,12 +62,12 @@ module clkmgr_mmcm
    //
  
    (* BUFFER_TYPE="NONE" *)
-	wire        clk_in_ibufg;

+	wire        gclk_in_ibufg;

 	
 	IBUFG IBUFG_gclk

    (

-		.I (clk_in),

-		.O	(clk_in_ibufg)

+		.I (gclk_in),

+		.O	(gclk_in_ibufg)

 	);

 
 

@@ -80,7 +81,7 @@ module clkmgr_mmcm
 	

 	MMCME2_ADV #

 	(

-		.CLKIN1_PERIOD        (20.000),

+		.CLKIN1_PERIOD        (11.111),

 		.REF_JITTER1          (0.010),

 

 		.STARTUP_WAIT         ("FALSE"),

@@ -94,7 +95,7 @@ module clkmgr_mmcm
 		.CLKFBOUT_USE_FINE_PS ("FALSE"),

 		

 		.CLKOUT0_DIVIDE_F     (CLK_OUT_DIV),

-		.CLKOUT0_PHASE        (0.000),

+		.CLKOUT0_PHASE        (CLK_OUT_PHI),

 		.CLKOUT0_USE_FINE_PS  ("FALSE"),

 		.CLKOUT0_DUTY_CYCLE   (0.500),

 		

@@ -102,7 +103,7 @@ module clkmgr_mmcm
 	)

 	MMCME2_ADV_inst

 	(

-		.CLKIN1              (clk_in_ibufg),

+		.CLKIN1              (gclk_in_ibufg),

 		.CLKIN2              (1'b0),

 		.CLKINSEL            (1'b1),

 

@@ -151,7 +152,7 @@ module clkmgr_mmcm
 	//
 	// Mapping
 	//
-	assign	gclk_out        = clk_in_ibufg;
+	assign	gclk_out        = gclk_in_ibufg;
 	assign	clk_valid_out   = mmcm_locked;