New Alpha platform with three clocks:

 *  45 MHz (aka "io_clk") is the I/O clock for the FMC bus
 *  90 MHz (aka "sys_clk") is the system clock for all the cores
 * 180 MHz (aka "core_clk") is the high-speed clock for high-performance cores

1 files changed, 69 insertions, 0 deletions

diff --git a/rtl/clkmgr_reset_gen.v b/rtl/clkmgr_reset_gen.v
new file mode 100644
index 0000000..9cc4401
--- /dev/null
+++ b/rtl/clkmgr_reset_gen.v
@@ -0,0 +1,69 @@
+//======================================================================
+//
+// clkmgr_reset_gen.v
+// ------------------
+// System reset generator.
+//
+//
+// Author: Pavel Shatov
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module clkmgr_reset_gen
+(
+    input  clk_in,
+    input  locked_in,
+    output reset_n_out
+);
+
+    //
+    // Parameter
+    //
+    parameter integer SHREG_WIDTH = 16;
+
+    //
+    // Shift Register
+    //
+    (* SHREG_EXTRACT="NO" *)
+    (* EQUIVALENT_REGISTER_REMOVAL="NO" *)
+    reg [SHREG_WIDTH-1:0] sys_rst_shreg = {SHREG_WIDTH{1'b0}};
+
+    always @(posedge clk_in or negedge locked_in)
+        //
+        if (!locked_in) sys_rst_shreg <= {SHREG_WIDTH{1'b0}};
+        else            sys_rst_shreg <= {sys_rst_shreg[SHREG_WIDTH-2:0], 1'b1};
+
+    assign reset_n_out = sys_rst_shreg[SHREG_WIDTH-1];
+
+endmodule
+
+//======================================================================
+// EOF clkmgr_reset_gen.v
+//======================================================================