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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-06-14 09:48:28 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-06-14 09:48:28 +0200 |
| commit | f34e44c3b2db29ad536e6c4a6792fbb7c0581164 (patch) | |
| tree | bcd05b58fdd161b8f0283cd77976ccad5e692333 /build/xilinx.mk | |
| parent | a4e91b6221f75045dd1d97362e9d12c590ebc15a (diff) | |
(1) Added ports and constraints for the gpio banks connected to the FPGA. (2) Added toggle circuit that generates a divided down version of the internal sys_clk. This divided clock is presented on pin 0 of both gpio banks.
Diffstat (limited to 'build/xilinx.mk')
0 files changed, 0 insertions, 0 deletions