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authorPaul Selkirk <paul@psgd.org>2019-01-22 19:39:09 -0500
committerPaul Selkirk <paul@psgd.org>2019-01-22 19:39:09 -0500
commitfe3d53cbd84a1a96ec93427a07f27321c4edaa6a (patch)
tree38f0b487b259e2e066c699b6724297ca917e392f /build/Makefile
parent50255f2ca56ad78df263207034e541d8aa284f12 (diff)
Upon reflection, I prefer the way Pavel handled include paths in 8cd28d0
(which he only committed on fmc_clk, and I was only looking at master). But I moved the curly brackets from Makefile to xilinx.mk, because a) Makefile shouldn't need to know the picky details of xst option syntax, and b) xst will throw an uninformative error if called with '-vlgincdir ' versus '-vlgincdir {}', if vlgincdir isn't defined in Makefile.
Diffstat (limited to 'build/Makefile')
-rw-r--r--build/Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/build/Makefile b/build/Makefile
index fc3a45b..0c61dba 100644
--- a/build/Makefile
+++ b/build/Makefile
@@ -18,6 +18,10 @@ isedir = /opt/Xilinx/14.7/ISE_DS
xil_env = . $(isedir)/settings$(WORD_SIZE).sh
ucf ?= ../ucf/$(project).ucf
+# Verilog include directories, if needed
+
+vlgincdir = $(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode
+
all: $(project).bit
# Build the default core_selector if it doesn't already exist.