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| author | Paul Selkirk <paul@psgd.org> | 2018-08-27 16:59:34 -0400 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2018-08-27 16:59:34 -0400 |
| commit | 7be8f9437441b07793e3b0f2a220cb15cc206354 (patch) | |
| tree | 12858f7b817911bf000eb75a95065a40aa333493 | |
| parent | a4e91b6221f75045dd1d97362e9d12c590ebc15a (diff) | |
correct fpga part number, add keywrap build target
| -rw-r--r-- | build/Makefile | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/build/Makefile b/build/Makefile index 4e3a9bb..8115637 100644 --- a/build/Makefile +++ b/build/Makefile @@ -12,7 +12,7 @@ WORD_SIZE := $(shell python -c 'from struct import pack; print len(pack("L", 0)) project ?= alpha_fmc vendor = xilinx family = artix7 -part = xc7a200tfbg484-3 +part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh @@ -60,6 +60,10 @@ hsm-super: $(CONFIG_GEN) -p hsm-super $(MAKE) project=$(project)_hsm-super ucf=$(ucf) +keywrap: + $(CONFIG_GEN) -p keywrap + $(MAKE) project=$(project)_keywrap ucf=$(ucf) + # Verilog files that always go with builds on this platform. vfiles = \ |