(1) Added ports and constraints for the gpio banks connected to the FPGA. (2) Added toggle circuit that generates a divided down version of the internal sys_clk. This divided clock is presented on pin 0 of both gpio banks.

2 files changed, 93 insertions, 19 deletions

diff --git a/rtl/alpha_fmc_top.v b/rtl/alpha_fmc_top.v
index 03c2802..a86a2c6 100644
--- a/rtl/alpha_fmc_top.v
+++ b/rtl/alpha_fmc_top.v
@@ -60,11 +60,19 @@ module alpha_fmc_top
    input wire 	      mkm_do,
    output wire 	      mkm_di,
 
+   output wire [7: 0] gpio_a,
+   output wire [7: 0] gpio_b,
    output wire [3: 0] led_pins  // {red, yellow, green, blue}
    );
 
 
    //----------------------------------------------------------------
+   // Dummy assignments to bypass unconnected outpins pins check in BitGen
+   //----------------------------------------------------------------
+   assign led_pins[3:1] = 3'b000;
+
+
+   //----------------------------------------------------------------
    // Clock Manager
    //
    // Clock manager is used to generate SYS_CLK from GCLK
@@ -81,7 +89,7 @@ module alpha_fmc_top
    clkmgr
      (
       .gclk      (gclk_pin),
-      
+
       .sys_clk   (sys_clk),
       .sys_rst_n (sys_rst_n)
       );
@@ -179,14 +187,62 @@ module alpha_fmc_top
       .mkm_cs_n(mkm_cs_n),
       .mkm_do(mkm_do),
       .mkm_di(mkm_di)
-      );  
-
-
-   //
-   // Dummy assignment to bypass unconnected outpins pins check in BitGen
-   //
-   
-   assign led_pins[3:1] = 3'b000;
+      );
 
 
-endmodule
+  //----------------------------------------------------------------
+  // sys_clk_toggle
+  //
+  // Simple circuit that allows observation of the sys_clk on
+  // an output pin. The sys_clk is divided down to allow
+  // measurement with simple equipment.
+  //
+  // One toggle cycle will be 2 * TOGGLE_DELAY_CYCLES. The
+  // number of cycles are selected to generate a 500 kHz period
+  // when sys_clk is running at 50 MHz.
+  //
+  // The toggle signal is presented at pin 0 of both GPIO banks
+  // available to the FPGA on the Alpha board.
+  //----------------------------------------------------------------
+  localparam TOGGLE_DELAY_CYCLES = 50;
+
+  reg [15 : 0] toggle_ctr_reg;
+  reg [15 : 0] toggle_ctr_new;
+
+  reg toggle_reg;
+  reg toggle_we;
+
+  assign gpio_a = {7'b0101010, toggle_reg};
+  assign gpio_b = {7'b1010101, toggle_reg};
+
+  always @(posedge sys_clk)
+    begin: sys_clk_toggle_reg_update
+      if (!reset_n)
+        begin
+          toggle_ctr_reg <= 16'h0;
+          toggle_reg     <= 1'b0;
+        end
+      else
+        begin
+          toggle_ctr_reg <= toggle_ctr_new;
+
+          if (toggle_we)
+            toggle_reg <= ~toggle_reg;
+        end
+    end
+
+  always @*
+    begin : sys_clk_toggle
+      if (toggle_ctr_reg == TOGGLE_DELAY_CYCLES)
+        begin
+          toggle_ctr_new = 16'h0;
+          toggle_we      = 1'b1;
+        end
+      else
+        begin
+          toggle_ctr_new = toggle_ctr_reg + 1'b1;
+          toggle_we      = 1'b0;
+        end
+    end
+
+endmodule // alpha_fmc_top
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf
index 5e71c64..9ed68fd 100644
--- a/ucf/alpha_fmc.ucf
+++ b/ucf/alpha_fmc.ucf
@@ -55,15 +55,33 @@ TIMESPEC  TS_fmc_clk = PERIOD TNM_fmc_clk 90 MHz HIGH 50%;
 #-------------------------------------------------------------------------------
 # FPGA Pinout
 #-------------------------------------------------------------------------------
-#

-NET "led_pins<0>" LOC = "U3";
-NET "led_pins<1>" LOC = "T1";
-NET "led_pins<2>" LOC = "W22";
-NET "led_pins<3>" LOC = "AA20";
-#
-NET "led_pins<*>" IOSTANDARD = "LVCMOS33";
-NET "led_pins<*>" SLEW = SLOW;
-NET "led_pins<*>" DRIVE = 8;
+# LEDs
+NET "led_pins<0>"       LOC = "U3"   | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+NET "led_pins<1>"       LOC = "T1"   | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+NET "led_pins<2>"       LOC = "W22"  | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+NET "led_pins<3>"       LOC = "AA20" | IOSTANDARD = "LVCMOS33" | SLEW = "SLOW" | DRIVE = 8;
+
+
+# GPIOs. Two banks
+NET  "fpga_gpio_a0"     LOC = "C15"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a1"     LOC = "E13"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a2"     LOC = "E14"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a3"     LOC = "E16"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a4"     LOC = "D16"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a5"     LOC = "D14"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a6"     LOC = "D15"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_a7"     LOC = "B15"  | IOSTANDARD = "LVCMOS33" ;
+
+NET  "fpga_gpio_b0"     LOC = "B16"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b1"     LOC = "C13"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b2"     LOC = "B13"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b3"     LOC = "A15"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b4"     LOC = "A16"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b5"     LOC = "A13"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b6"     LOC = "A14"  | IOSTANDARD = "LVCMOS33" ;
+NET  "fpga_gpio_b7"     LOC = "B17"  | IOSTANDARD = "LVCMOS33" ;
+
+
 #
 NET  "gclk_pin"        LOC = "D17"  | IOSTANDARD = "LVCMOS33" ;
 #