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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:49:30 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:50:04 +0300 |
| commit | e5e51b4db3ae127522eac031b7662f901ae803cc (patch) | |
| tree | ae3d15679e0abc7180cef512df911a42ccfa040f | |
| parent | 2e3c424a3c155a0343f96ca5894f816f515bede6 (diff) | |
Ignore timing for async reset.
| -rw-r--r-- | ucf/alpha_fmc.ucf | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ucf/alpha_fmc.ucf b/ucf/alpha_fmc.ucf index efefa76..99ab040 100644 --- a/ucf/alpha_fmc.ucf +++ b/ucf/alpha_fmc.ucf @@ -51,6 +51,8 @@ NET "fmc_clk" TNM_NET = TNM_fmc_clk; TIMESPEC TS_fmc_clk = PERIOD TNM_fmc_clk 11.111 ns HIGH 50%; +NET "clkmgr/sys_rst_shreg[15]" TNM_NET = TNM_sys_rst_shreg15; +TIMESPEC TS_sys_rst_tig = FROM TNM_sys_rst_shreg15 TIG; #------------------------------------------------------------------------------- # FPGA Pinout |