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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:47:33 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-12-19 15:47:33 +0300 |
| commit | 8cd28d0fc12f0671ae3af89209de52a159d8cf19 (patch) | |
| tree | 7aee60c63fa75b88b1e047748342be1e8d09a1bb | |
| parent | f8f86f9cfbd0ac73d2b0d3600e424b9c669cea59 (diff) | |
Added `include directories to Makefile
| -rw-r--r-- | build/Makefile | 6 | ||||
| -rw-r--r-- | build/xilinx.mk | 1 |
2 files changed, 6 insertions, 1 deletions
diff --git a/build/Makefile b/build/Makefile index f573ace..5a6107d 100644 --- a/build/Makefile +++ b/build/Makefile @@ -16,7 +16,11 @@ part = xc7a200tfbg484-1 top_module = alpha_fmc_top isedir = /opt/Xilinx/14.7/ISE_DS xil_env = . $(isedir)/settings$(WORD_SIZE).sh -ucf ?= ../ucf/$(project).ucf +ucf ?= ../ucf/$(project).ucf + +# verilog include directories {yes, XST wants them exactly this way in curly braces} +vlgincdir = {$(CORE_TREE)/lib/lowlevel $(CORE_TREE)/math/ecdsalib/rtl/microcode} + all: $(project).bit diff --git a/build/xilinx.mk b/build/xilinx.mk index 9af9366..c88f00b 100644 --- a/build/xilinx.mk +++ b/build/xilinx.mk @@ -155,6 +155,7 @@ $(project).scr: $(optfile) $(mkfiles) ./xilinx.opt echo "-ifn $(project).prj" >> $@ echo "-ofn $(project).ngc" >> $@ cat ./xilinx.opt $(optfile) >> $@ + echo "-vlgincdir $(vlgincdir)" >> $@ junk += $(project).scr $(project).post_map.twr: $(project).ncd |