aboutsummaryrefslogblamecommitdiff
path: root/build/config.py
blob: e737c92bbdedea159e568ec5618d05cd3f7bdc78 (plain) (tree)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573




























































































































































































































































































































































































































































































































































































                                                                                                                                                                                  
#!/usr/bin/env python

"""
Generate core_selector.v and core_vfiles.mk for a set of cores.
"""

#=======================================================================
# Copyright (c) 2015-2016, NORDUnet A/S All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
# - Redistributions of source code must retain the above copyright notice,
#   this list of conditions and the following disclaimer.
#
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
#
# - Neither the name of the NORDUnet nor the names of its contributors may
#   be used to endorse or promote products derived from this software
#   without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#=======================================================================

# The modexpa7 core drags in a one clock cycle delay to other cores,
# to compensate for the extra clock cycle consumed by the block
# memories used in the modexpa7 core.  We probably want a general
# solution for this, because we're going to run into this problem for
# any core that handles arguments big enough to require block memory.

# To Do:
#
# - Consider automating the one-clock-cycle delay stuff by adding
#   another boolean flag to the config file.  Default would be no
#   delay, if any included core sets the "I use block memories" flag,
#   all other cores would get the delay.  Slightly tedious but
#   something we can calculate easily enough, and probably an
#   improvement over wiring in the delay when nothing needs it.
#
# - Rename script and its config file to something more meaningful.


def main():
    """
    Parse arguments and config file, generate core list, generate output.
    """

    from argparse import ArgumentParser, FileType, ArgumentDefaultsHelpFormatter
    from sys      import exit

    parser = ArgumentParser(description = __doc__, formatter_class = ArgumentDefaultsHelpFormatter)
    parser.add_argument("-d", "--debug",   help = "enable debugging",   action = "store_true")
    parser.add_argument("-s", "--section", help = "config file section")
    parser.add_argument("-c", "--config",  help = "configuration file",   default = "config.cfg",       type = FileType("r"))
    parser.add_argument("--verilog",       help = "verilog output file",  default = "core_selector.v",  type = FileType("w"))
    parser.add_argument("--makefile",      help = "output makefile",      default = "core_vfiles.mk",   type = FileType("w"))
    parser.add_argument("core",            help = "name(s) of core(s)", nargs = "*")
    args = parser.parse_args()

    try:
        cfg = RawConfigParser()
        cfg.readfp(args.config)

        if args.core:
            cores = args.core
        else:
            section = args.section or cfg.get("default", "default-section")
            cores = cfg.get(section, "cores").split()

        cores.insert(0, "board_regs")
        cores.insert(1, "comm_regs")

        cores = tuple(Core.new(core) for core in cores)

        core_number = 0
        for core in cores:
            core_number = core.assign_core_number(core_number)

        for core in cores:
            core.configure(cfg)

        if False:

            # For some reason, attempting to optimize out the delay
            # code entirely results in a non-working bitstream.  Don't
            # know why, disabling the optimization works, so just do
            # that for now.

            Core.need_one_cycle_delay = any(core.block_memory for core in cores)

        args.verilog.write(createModule_template.format(
            addrs = "".join(core.createAddr()     for core in cores),
            insts = "".join(core.createInstance() for core in cores),
            muxes = "".join(core.createMux()      for core in cores),
            ports = "".join(core.createPort()     for core in cores) ))

        args.makefile.write(listVfiles_template.format(
            vfiles = "".join(core.listVfiles()    for core in cores)))

    except Exception, e:
        if args.debug:
            raise
        exit(str(e))


try:
    import ConfigParser as configparser
except ImportError:
    import configparser   

class RawConfigParser(configparser.RawConfigParser):
    """
    RawConfigParser with a few extensions.
    """

    def getboolean(self, section, option, default = False):
        if self.has_option(section, option):
            # RawConfigParser is an old-stle class, super() doesn't work, feh.
            return configparser.RawConfigParser.getboolean(self, section, option)
        else:
            return default

    def getvalues(self, section, option):
        if self.has_option(section, option):
            for value in self.get(section, option).split():
                yield value


class Core(object):
    """
    Data and methods for a generic core.  We can use this directly for
    most cores, a few are weird and require subclassing to override
    particular methods.
    """

    # Class variable tracking how many times a particular core has
    # been instantiated.  This controls instance numbering.

    _instance_count = {}

    # Class variable mapping core name to subclass for special cases.

    special_class = {}

    # Class variable recording whether we need a one-cycle delay to
    # compensate for block memories.

    need_one_cycle_delay = True

    def __init__(self, name):
        self.name = name
        self.core_number = None
        self.vfiles = []
        self.error_wire = True
        self.block_memory = False
        self.instance_number = self._instance_count.get(name, 0)
        self._instance_count[name] = self.instance_number + 1

    @classmethod
    def new(cls, name):
        return cls.special_class.get(name, cls)(name)

    def assign_core_number(self, n):
        self.core_number = n
        return n + 1

    def configure(self, cfg):
        if self.instance_number == 0:
            self.vfiles.extend(cfg.getvalues(self.name, "vfiles"))
            for required in cfg.getvalues(self.name, "requires"):
                if required not in self._instance_count:
                    self.vfiles.extend(cfg.getvalues(required, "vfiles"))
        self.error_wire = cfg.getboolean(self.name, "error_wire", self.error_wire)
        self.block_memory = cfg.getboolean(self.name, "block_memory", self.block_memory)

    @property
    def instance_name(self):
        if self._instance_count[self.name] > 1:
            return "{}_{}".format(self.name, self.instance_number)
        else:
            return self.name

    @property
    def upper_instance_name(self):
        return self.instance_name.upper()

    @property
    def reset_pin(self):
        return ".reset_n(sys_rst_n)"

    @property
    def error_port(self):
        return ",\n      .error(error_{core.instance_name})".format(core = self) if self.error_wire else ""

    @property
    def one_cycle_delay(self):
        return one_cycle_delay_template.format(core = self) if self.need_one_cycle_delay and not self.block_memory else ""

    @property
    def mux_data_reg(self):
        return "read_data_" + self.instance_name + ("_reg" if self.need_one_cycle_delay and not self.block_memory else "")

    @property
    def mux_error_reg(self):
        return "error_" + self.instance_name if self.error_wire else "0"

    def createInstance(self):
        return createInstance_template_generic.format(core = self)

    def createAddr(self):
        return createAddr_template.format(core = self)

    def createMux(self):
        return createMux_template.format(core = self, core0 = self)

    def createPort(self):
        return ""

    def listVfiles(self):
        return "".join(" \\\n\t$(CORE_TREE)/" + vfile for vfile in self.vfiles)


class SubCore(Core):
    """"
    Override mux handling for TRNG's sub-cores.
    """

    def __init__(self, name, parent):
        super(SubCore, self).__init__(name)
        self.parent = parent

    def createMux(self):
        return createMux_template.format(core = self, core0 = self.parent)


class TRNGCore(Core):
    """
    The TRNG core has an internal mux with slots for 15 sub-cores,
    most of which are empty.  This is a bit of a mess.

    Mostly this means that our method calls have to iterate over all
    of the subcores after handling the base TRNG core, but we also use
    different templates, and fiddle with addresses a bit.

    Mux numbers have to be dug out of the TRNG Verilog source.
    """

    # TRNG subcore name -> internal mux number.
    subcore_parameters = dict(avalanche_entropy = 0x1,
                              rosc_entropy      = 0x2,
                              trng_mixer        = 0x3,
                              trng_csprng       = 0x4)

    def __init__(self, name):
        super(TRNGCore, self).__init__(name)
        self.subcores = tuple(SubCore(name, self)
                              for name in sorted(self.subcore_parameters,
                                                 key = lambda x: self.subcore_parameters[x]))

    def assign_core_number(self, n):
        n = super(TRNGCore, self).assign_core_number(n)
        for subcore in self.subcores:
            subcore.assign_core_number(self.core_number + self.subcore_parameters[subcore.name])
        return n + 15

    @property
    def last_subcore_upper_instance_name(self):
        return self.subcores[-1].upper_instance_name

    def createInstance(self):
        return createInstance_template_TRNG.format(core = self)

    def createAddr(self):
        return super(TRNGCore, self).createAddr() + "".join(subcore.createAddr() for subcore in self.subcores)

    def createMux(self):
        return super(TRNGCore, self).createMux() + "".join(subcore.createMux() for subcore in self.subcores)


class ModExpA7Core(Core):
    """
    ModExpA7 core consumes as much space as four ordinary cores, and
    uses different templates to handle the differences in timing and
    addressing.
    """

    def assign_core_number(self, n):
        n = super(ModExpA7Core, self).assign_core_number(n)
        return n + 3

    def createInstance(self):
        return createInstance_template_ModExpA7.format(core = self)

    def createMux(self):
        return createMux_modexpa7_template.format(core = self, core0 = self)

class MkmifCore(Core):
    """
    MKM interface core has extra ports for the SPI signal lines.
    """

    def createPort(self):
        return """ \

   output wire         mkm_sclk,
   output wire         mkm_cs_n,
   input wire          mkm_do,
   output wire         mkm_di,
        """

    def createInstance(self):
        return createInstance_template_MKMIF.format(core = self)

# Hook special classes in as handlers for the cores that require them.

Core.special_class.update(
    trng        = TRNGCore,
    modexpa7    = ModExpA7Core,
    mkmif       = MkmifCore)


# Templates (format strings), here instead of inline in the functions
# that use them, both because some of these are shared between
# multiple functions and because it's easier to read these (and get
# the indentation right) when the're separate.

# Template used by .createAddr() methods.

createAddr_template = """\
   localparam   CORE_ADDR_{core.upper_instance_name:21s} = 15'h{core.core_number:02x};
"""

# Template used by Core.createInstance().

createInstance_template_generic = """\
   //----------------------------------------------------------------
   // {core.upper_instance_name}
   //----------------------------------------------------------------
   wire                 enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
   wire [31: 0]         read_data_{core.instance_name};
   wire                 error_{core.instance_name};

   {core.name} {core.instance_name}_inst
     (
      .clk(sys_clk),
      {core.reset_pin},

      .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
      .we(sys_fmc_wr),

      .address(addr_core_reg),
      .write_data(sys_write_data),
      .read_data(read_data_{core.instance_name}){core.error_port}
      );

{core.one_cycle_delay}

"""

# Template used by ModExpA7Core.createInstance().  This is different
# enough from the base template that it's easier to make this separate.

createInstance_template_ModExpA7 = """\
   //----------------------------------------------------------------
   // {core.upper_instance_name}
   //----------------------------------------------------------------
   wire                 enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 15'h03);
   wire [31: 0]         read_data_{core.instance_name};
   wire [1:0]           {core.instance_name}_prefix = addr_core_num[1:0] - CORE_ADDR_{core.upper_instance_name};

   {core.name}_wrapper {core.instance_name}_inst
     (
      .clk(sys_clk),
      {core.reset_pin},

      .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
      .we(sys_fmc_wr),

      .address({{{core.instance_name}_prefix, addr_core_reg}}),
      .write_data(sys_write_data),
      .read_data(read_data_{core.instance_name})
      );


"""

# Template used by TRNGCore.createInstance(); this is different enough
# from the generic template that it's (probably) clearer to have this
# separate.

createInstance_template_TRNG = """\
   //----------------------------------------------------------------
   // {core.upper_instance_name}
   //----------------------------------------------------------------
   wire                 enable_{core.instance_name} = (addr_core_num >= CORE_ADDR_{core.upper_instance_name}) && (addr_core_num <= CORE_ADDR_{core.upper_instance_name} + 15'h0f);
   wire [31: 0]         read_data_{core.instance_name};
   wire                 error_{core.instance_name};
   wire [3:0]           {core.instance_name}_prefix = addr_core_num[3:0] - CORE_ADDR_{core.upper_instance_name};

   {core.name} {core.instance_name}_inst
     (
      .clk(sys_clk),
      {core.reset_pin},

      .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
      .we(sys_fmc_wr),

      .address({{{core.instance_name}_prefix, addr_core_reg}}),
      .write_data(sys_write_data),
      .read_data(read_data_{core.instance_name}),
      .error(error_{core.instance_name}),

      .avalanche_noise(noise),
      .debug(debug)
      );

{core.one_cycle_delay}

"""

# Template used by Mkmif.createInstance().  This is different
# enough from the base template that it's easier to make this separate.

createInstance_template_MKMIF = """\
   //----------------------------------------------------------------
   // {core.upper_instance_name}
   //----------------------------------------------------------------
   wire                 enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
   wire [31: 0]         read_data_{core.instance_name};

   {core.name} {core.instance_name}_inst
     (
      .clk(sys_clk),
      {core.reset_pin},

      .spi_sclk(mkm_sclk),
      .spi_cs_n(mkm_cs_n),
      .spi_do(mkm_do),
      .spi_di(mkm_di),

      .cs(enable_{core.instance_name} & (sys_fmc_rd | sys_fmc_wr)),
      .we(sys_fmc_wr),

      .address(addr_core_reg),
      .write_data(sys_write_data),
      .read_data(read_data_{core.instance_name}){core.error_port}
      );

{core.one_cycle_delay}

"""

# Template for one-cycle delay code.

one_cycle_delay_template = """\
   reg  [31: 0] read_data_{core.instance_name}_reg;
   always @(posedge sys_clk)
     read_data_{core.instance_name}_reg <= read_data_{core.instance_name};
"""

# Template for .createMux() methods.

createMux_template = """\
       CORE_ADDR_{core.upper_instance_name}:
         begin
            sys_read_data_mux = {core0.mux_data_reg};
            sys_error_mux = {core0.mux_error_reg};
         end
"""

# Template for ModExpA7.createMux() method.

createMux_modexpa7_template = """\
       CORE_ADDR_{core.upper_instance_name} + 0,
       CORE_ADDR_{core.upper_instance_name} + 1,
       CORE_ADDR_{core.upper_instance_name} + 2,
       CORE_ADDR_{core.upper_instance_name} + 3:
         begin
            sys_read_data_mux = {core0.mux_data_reg};
            sys_error_mux = {core0.mux_error_reg};
         end
"""


# Top-level (createModule) template.

createModule_template = """\
// NOTE: This file is generated; do not edit by hand.

module core_selector
  (
   input wire          sys_clk,
   input wire          sys_rst_n,

   input wire [23: 0]  sys_fmc_addr,
   input wire          sys_fmc_wr,
   input wire          sys_fmc_rd,
   output wire [31: 0] sys_read_data,
   input wire [31: 0]  sys_write_data,
   output wire         sys_error,
{ports}
   input wire          noise,
   output wire [7 : 0] debug
   );


   //----------------------------------------------------------------
   // Address Decoder
   //----------------------------------------------------------------
   // upper 15 bits specify core being addressed
   wire [14: 0]         addr_core_num   = sys_fmc_addr[23: 8];
   // lower 8 bits specify register offset in core
   wire [ 7: 0]         addr_core_reg   = sys_fmc_addr[ 7: 0];


   //----------------------------------------------------------------
   // Core Address Table
   //----------------------------------------------------------------
{addrs}

{insts}
   //----------------------------------------------------------------
   // Output (Read Data) Multiplexer
   //----------------------------------------------------------------
   reg [31: 0]          sys_read_data_mux;
   assign               sys_read_data = sys_read_data_mux;
   reg                  sys_error_mux;
   assign               sys_error = sys_error_mux;

   always @*

     case (addr_core_num)
{muxes}
       default:
         begin
            sys_read_data_mux = {{32{{1'b0}}}};
            sys_error_mux = 1;
         end
     endcase


endmodule


//======================================================================
// EOF core_selector.v
//======================================================================
"""

# Template for makefile snippet listing Verilog source files.

listVfiles_template = """\
# NOTE: This file is generated; do not edit by hand.

vfiles +={vfiles}
"""

# Run main program.

if __name__ == "__main__":
    main()