diff options
Diffstat (limited to 'rtl/ed25519_multiplier.v')
| -rw-r--r-- | rtl/ed25519_multiplier.v | 121 |
1 files changed, 100 insertions, 21 deletions
diff --git a/rtl/ed25519_multiplier.v b/rtl/ed25519_multiplier.v index d6960ec..31a4b18 100644 --- a/rtl/ed25519_multiplier.v +++ b/rtl/ed25519_multiplier.v @@ -72,19 +72,31 @@ module ed25519_multiplier // // FSM // - localparam [3:0] FSM_STATE_IDLE = 4'd00; - localparam [3:0] FSM_STATE_PREPARE_TRIG = 4'd01; - localparam [3:0] FSM_STATE_PREPARE_WAIT = 4'd02; - localparam [3:0] FSM_STATE_BEFORE_ROUND_TRIG = 4'd03; - localparam [3:0] FSM_STATE_BEFORE_ROUND_WAIT = 4'd04; - localparam [3:0] FSM_STATE_DURING_ROUND_TRIG = 4'd05; - localparam [3:0] FSM_STATE_DURING_ROUND_WAIT = 4'd06; - localparam [3:0] FSM_STATE_AFTER_ROUND_TRIG = 4'd07; - localparam [3:0] FSM_STATE_AFTER_ROUND_WAIT = 4'd08; - localparam [3:0] FSM_STATE_DONE = 4'd15; - - reg [3:0] fsm_state = FSM_STATE_IDLE; - reg [3:0] fsm_state_next; + localparam [4:0] FSM_STATE_IDLE = 5'd00; + localparam [4:0] FSM_STATE_PREPARE_TRIG = 5'd01; + localparam [4:0] FSM_STATE_PREPARE_WAIT = 5'd02; + localparam [4:0] FSM_STATE_BEFORE_ROUND_TRIG = 5'd03; + localparam [4:0] FSM_STATE_BEFORE_ROUND_WAIT = 5'd04; + localparam [4:0] FSM_STATE_DURING_ROUND_TRIG = 5'd05; + localparam [4:0] FSM_STATE_DURING_ROUND_WAIT = 5'd06; + localparam [4:0] FSM_STATE_AFTER_ROUND_TRIG = 5'd07; + localparam [4:0] FSM_STATE_AFTER_ROUND_WAIT = 5'd08; + localparam [4:0] FSM_STATE_BEFORE_INVERT_TRIG = 5'd09; + localparam [4:0] FSM_STATE_BEFORE_INVERT_WAIT = 5'd10; + localparam [4:0] FSM_STATE_DURING_INVERT_TRIG = 5'd11; + localparam [4:0] FSM_STATE_DURING_INVERT_WAIT = 5'd12; + localparam [4:0] FSM_STATE_AFTER_INVERT_TRIG = 5'd13; + localparam [4:0] FSM_STATE_AFTER_INVERT_WAIT = 5'd14; + localparam [4:0] FSM_STATE_FINAL_REDUCE_TRIG = 5'd15; + localparam [4:0] FSM_STATE_FINAL_REDUCE_WAIT = 5'd16; + localparam [4:0] FSM_STATE_HANDLE_SIGN_TRIG = 5'd17; + localparam [4:0] FSM_STATE_HANDLE_SIGN_WAIT = 5'd18; + localparam [4:0] FSM_STATE_OUTPUT_TRIG = 5'd19; + localparam [4:0] FSM_STATE_OUTPUT_WAIT = 5'd20; + localparam [4:0] FSM_STATE_DONE = 5'd31; + + reg [4:0] fsm_state = FSM_STATE_IDLE; + reg [4:0] fsm_state_next; // @@ -114,7 +126,13 @@ module ed25519_multiplier FSM_STATE_PREPARE_TRIG, FSM_STATE_BEFORE_ROUND_TRIG, FSM_STATE_DURING_ROUND_TRIG, - FSM_STATE_AFTER_ROUND_TRIG: worker_trig <= 1'b1; + FSM_STATE_AFTER_ROUND_TRIG, + FSM_STATE_BEFORE_INVERT_TRIG, + FSM_STATE_DURING_INVERT_TRIG, + FSM_STATE_AFTER_INVERT_TRIG, + FSM_STATE_FINAL_REDUCE_TRIG, + FSM_STATE_HANDLE_SIGN_TRIG, + FSM_STATE_OUTPUT_TRIG: worker_trig <= 1'b1; default: worker_trig <= 1'b0; endcase @@ -134,10 +152,8 @@ module ed25519_multiplier // Final Round Detection Logic // wire [ 3: 0] fsm_state_after_round = (bit_counter != bit_counter_zero) ? - FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_DONE; - - - + FSM_STATE_BEFORE_ROUND_TRIG : FSM_STATE_BEFORE_INVERT_TRIG; + // // K Latch @@ -171,6 +187,14 @@ module ed25519_multiplier case (fsm_state) FSM_STATE_PREPARE_TRIG: worker_offset <= UOP_OFFSET_PREPARE; FSM_STATE_BEFORE_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_BEFORE_ROUND_K1 : UOP_OFFSET_BEFORE_ROUND_K0; + FSM_STATE_DURING_ROUND_TRIG: worker_offset <= UOP_OFFSET_DURING_ROUND; + FSM_STATE_AFTER_ROUND_TRIG: worker_offset <= k_din_shreg[0] ? UOP_OFFSET_AFTER_ROUND_K1 : UOP_OFFSET_AFTER_ROUND_K0; + FSM_STATE_BEFORE_INVERT_TRIG: worker_offset <= UOP_OFFSET_BEFORE_INVERSION; + FSM_STATE_DURING_INVERT_TRIG: worker_offset <= UOP_OFFSET_DURING_INVERSION; + FSM_STATE_AFTER_INVERT_TRIG: worker_offset <= UOP_OFFSET_AFTER_INVERSION; + FSM_STATE_FINAL_REDUCE_TRIG: worker_offset <= UOP_OFFSET_FINAL_REDUCTION; + FSM_STATE_HANDLE_SIGN_TRIG: worker_offset <= UOP_OFFSET_HANDLE_SIGN; + FSM_STATE_OUTPUT_TRIG: worker_offset <= UOP_OFFSET_OUTPUT; default: worker_offset <= {UOP_ADDR_WIDTH{1'bX}}; endcase @@ -207,6 +231,24 @@ module ed25519_multiplier FSM_STATE_AFTER_ROUND_TRIG: fsm_state_next = FSM_STATE_AFTER_ROUND_WAIT; FSM_STATE_AFTER_ROUND_WAIT: fsm_state_next = fsm_wait_done ? fsm_state_after_round : FSM_STATE_AFTER_ROUND_WAIT; + FSM_STATE_BEFORE_INVERT_TRIG: fsm_state_next = FSM_STATE_BEFORE_INVERT_WAIT; + FSM_STATE_BEFORE_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DURING_INVERT_TRIG : FSM_STATE_BEFORE_INVERT_WAIT; + + FSM_STATE_DURING_INVERT_TRIG: fsm_state_next = FSM_STATE_DURING_INVERT_WAIT; + FSM_STATE_DURING_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_AFTER_INVERT_TRIG : FSM_STATE_DURING_INVERT_WAIT; + + FSM_STATE_AFTER_INVERT_TRIG: fsm_state_next = FSM_STATE_AFTER_INVERT_WAIT; + FSM_STATE_AFTER_INVERT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_FINAL_REDUCE_TRIG : FSM_STATE_AFTER_INVERT_WAIT; + + FSM_STATE_FINAL_REDUCE_TRIG: fsm_state_next = FSM_STATE_FINAL_REDUCE_WAIT; + FSM_STATE_FINAL_REDUCE_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_HANDLE_SIGN_TRIG : FSM_STATE_FINAL_REDUCE_WAIT; + + FSM_STATE_HANDLE_SIGN_TRIG: fsm_state_next = FSM_STATE_HANDLE_SIGN_WAIT; + FSM_STATE_HANDLE_SIGN_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_OUTPUT_TRIG : FSM_STATE_HANDLE_SIGN_WAIT; + + FSM_STATE_OUTPUT_TRIG: fsm_state_next = FSM_STATE_OUTPUT_WAIT; + FSM_STATE_OUTPUT_WAIT: fsm_state_next = fsm_wait_done ? FSM_STATE_DONE : FSM_STATE_OUTPUT_WAIT; + FSM_STATE_DONE: fsm_state_next = FSM_STATE_IDLE; endcase @@ -214,16 +256,53 @@ module ed25519_multiplier end + // + // Debug + // + wire debug_dump_now = fsm_state == FSM_STATE_OUTPUT_TRIG; + + reg [6:0] debug_dump_addr1 = {1'bX, UOP_OPERAND_INVERT_R1}; + reg [6:0] debug_dump_addr2 = {1'b0, UOP_OPERAND_CYCLE_R0_X}; + reg [6:0] debug_dump_addr3 = {1'b0, UOP_OPERAND_CYCLE_R0_Y}; + reg [6:0] debug_dump_addr4 = {1'bX, UOP_OPERAND_CYCLE_R0_T}; + reg [6:0] debug_dump_addr5 = {1'bX, UOP_OPERAND_CYCLE_R1_X}; + reg [6:0] debug_dump_addr6 = {1'bX, UOP_OPERAND_CYCLE_R1_Y}; + reg [6:0] debug_dump_addr7 = {1'bX, UOP_OPERAND_CYCLE_R1_Z}; + reg [6:0] debug_dump_addr8 = {1'bX, UOP_OPERAND_CYCLE_R1_T}; + // // Worker // + + wire worker_final_reduce = fsm_state == FSM_STATE_FINAL_REDUCE_WAIT; + wire worker_handle_sign = fsm_state == FSM_STATE_HANDLE_SIGN_WAIT; + wire worker_output_now = fsm_state == FSM_STATE_OUTPUT_WAIT; + ed25519_worker uop_worker ( .clk (clk), .rst_n (rst_n), - .ena (worker_trig), - .rdy (worker_done), - .uop_offset (worker_offset) + .debug_dump_now (debug_dump_now), + + .debug_dump_addr1 (debug_dump_addr1), + .debug_dump_addr2 (debug_dump_addr2), + .debug_dump_addr3 (debug_dump_addr3), + .debug_dump_addr4 (debug_dump_addr4), + .debug_dump_addr5 (debug_dump_addr5), + .debug_dump_addr6 (debug_dump_addr6), + .debug_dump_addr7 (debug_dump_addr7), + .debug_dump_addr8 (debug_dump_addr8), + + .ena (worker_trig), + .rdy (worker_done), + .uop_offset (worker_offset), + .final_reduce (worker_final_reduce), + .handle_sign (worker_handle_sign), + .output_now (worker_output_now), + + .y_addr (qy_addr), + .y_dout (qy_dout), + .y_wren (qy_wren) ); |