diff options
Diffstat (limited to 'rtl/ed25519_microcode.v')
| -rw-r--r-- | rtl/ed25519_microcode.v | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/rtl/ed25519_microcode.v b/rtl/ed25519_microcode.v new file mode 100644 index 0000000..95f8fec --- /dev/null +++ b/rtl/ed25519_microcode.v @@ -0,0 +1,88 @@ +//====================================================================== +// +// Copyright (c) 2018, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//======================================================================`timescale 1ns 1ps + + +module ed25519_microcode +( + input wire clk, + input wire [UOP_ADDR_WIDTH-1:0] addr, + output reg [UOP_DATA_WIDTH-1:0] data +); + +`include "ed25519_uop.v" + + always @(posedge clk) + // + case (addr) + + // Initialization + 6'd00: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_X}; + 6'd01: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Y}; + 6'd02: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_Z}; + 6'd03: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ZERO, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R0_T}; + + 6'd04: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_X}; + 6'd05: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Y}; + 6'd06: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_ONE, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_Z}; + 6'd07: data <= {UOP_OPCODE_COPY, UOP_BANKS_HI2LO, UOP_OPERAND_CONST_G_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_R1_T}; + + 6'd08: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + + // Before Round when k = 1 + 6'd09: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; + 6'd10: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; + 6'd11: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; + 6'd12: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; + + 6'd13: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; + 6'd14: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; + 6'd15: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; + 6'd16: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; + + 6'd17: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + + // Before Round when k = 0 + 6'd18: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_X}; + 6'd19: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Y}; + 6'd20: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_Z}; + 6'd21: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R0_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_V_T}; + + 6'd22: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_X, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_X}; + 6'd23: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Y, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Y}; + 6'd24: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_Z, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_Z}; + 6'd25: data <= {UOP_OPCODE_COPY, UOP_BANKS_LO2HI, UOP_OPERAND_CYCLE_R1_T, UOP_OPERAND_DONTCARE, UOP_OPERAND_CYCLE_U_T}; + + 6'd26: data <= {UOP_OPCODE_STOP, UOP_BANKS_DUMMY, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE, UOP_OPERAND_DONTCARE}; + + endcase + +endmodule |