From c09de3ee3a303bfab596def8e0b5c8b845e5a97f Mon Sep 17 00:00:00 2001
From: Rob Austein <sra@hactrn.net>
Date: Tue, 7 Mar 2017 19:55:09 -0500
Subject: Promote to a repository in the core tree.

Change name of reset signal from rst_n to reset_n for consistancy with
other Cryptech cores.

Code common between this core and the ecdsa256 core split out into a
separate library repository.

Minor cleanup (Windows-isms, indentation).
---
 rtl/curve/rom/brom_p384_delta.v | 46 ++++++++++++++++++-------------------
 rtl/curve/rom/brom_p384_g_x.v   | 48 +++++++++++++++++++--------------------
 rtl/curve/rom/brom_p384_g_y.v   | 50 ++++++++++++++++++++---------------------
 rtl/curve/rom/brom_p384_h_x.v   | 46 ++++++++++++++++++-------------------
 rtl/curve/rom/brom_p384_h_y.v   | 48 +++++++++++++++++++--------------------
 rtl/curve/rom/brom_p384_one.v   | 46 ++++++++++++++++++-------------------
 rtl/curve/rom/brom_p384_q.v     | 50 ++++++++++++++++++++---------------------
 rtl/curve/rom/brom_p384_zero.v  | 10 ++++-----
 8 files changed, 172 insertions(+), 172 deletions(-)

(limited to 'rtl/curve/rom')

diff --git a/rtl/curve/rom/brom_p384_delta.v b/rtl/curve/rom/brom_p384_delta.v
index 754af3e..165b3d9 100644
--- a/rtl/curve/rom/brom_p384_delta.v
+++ b/rtl/curve/rom/brom_p384_delta.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_delta
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h80000000;
-			4'b0001:	bram_reg_b <= 32'h00000000;
-			4'b0010:	bram_reg_b <= 32'h80000000;
-			4'b0011:	bram_reg_b <= 32'h7fffffff;
-			4'b0100:	bram_reg_b <= 32'hffffffff;
-			4'b0101:	bram_reg_b <= 32'hffffffff;
-			4'b0110:	bram_reg_b <= 32'hffffffff;
-			4'b0111:	bram_reg_b <= 32'hffffffff;
-			4'b1000:	bram_reg_b <= 32'hffffffff;
-			4'b1001:	bram_reg_b <= 32'hffffffff;
-			4'b1010:	bram_reg_b <= 32'hffffffff;
-			4'b1011:	bram_reg_b <= 32'h7fffffff;
-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h80000000;
+       4'b0001:	bram_reg_b <= 32'h00000000;
+       4'b0010:	bram_reg_b <= 32'h80000000;
+       4'b0011:	bram_reg_b <= 32'h7fffffff;
+       4'b0100:	bram_reg_b <= 32'hffffffff;
+       4'b0101:	bram_reg_b <= 32'hffffffff;
+       4'b0110:	bram_reg_b <= 32'hffffffff;
+       4'b0111:	bram_reg_b <= 32'hffffffff;
+       4'b1000:	bram_reg_b <= 32'hffffffff;
+       4'b1001:	bram_reg_b <= 32'hffffffff;
+       4'b1010:	bram_reg_b <= 32'hffffffff;
+       4'b1011:	bram_reg_b <= 32'h7fffffff;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_g_x.v b/rtl/curve/rom/brom_p384_g_x.v
index 25d5103..614c7fe 100644
--- a/rtl/curve/rom/brom_p384_g_x.v
+++ b/rtl/curve/rom/brom_p384_g_x.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_g_x
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h72760ab7;
-			4'b0001:	bram_reg_b <= 32'h3a545e38;
-			4'b0010:	bram_reg_b <= 32'hbf55296c;
-			4'b0011:	bram_reg_b <= 32'h5502f25d;
-			4'b0100:	bram_reg_b <= 32'h82542a38;
-			4'b0101:	bram_reg_b <= 32'h59f741e0;
-			4'b0110:	bram_reg_b <= 32'h8ba79b98;
-			4'b0111:	bram_reg_b <= 32'h6e1d3b62;
-			4'b1000:	bram_reg_b <= 32'hf320ad74;
-			4'b1001:	bram_reg_b <= 32'h8eb1c71e;
-			4'b1010:	bram_reg_b <= 32'hbe8b0537;
-			4'b1011:	bram_reg_b <= 32'haa87ca22;
-		endcase
-		
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h72760ab7;
+       4'b0001:	bram_reg_b <= 32'h3a545e38;
+       4'b0010:	bram_reg_b <= 32'hbf55296c;
+       4'b0011:	bram_reg_b <= 32'h5502f25d;
+       4'b0100:	bram_reg_b <= 32'h82542a38;
+       4'b0101:	bram_reg_b <= 32'h59f741e0;
+       4'b0110:	bram_reg_b <= 32'h8ba79b98;
+       4'b0111:	bram_reg_b <= 32'h6e1d3b62;
+       4'b1000:	bram_reg_b <= 32'hf320ad74;
+       4'b1001:	bram_reg_b <= 32'h8eb1c71e;
+       4'b1010:	bram_reg_b <= 32'hbe8b0537;
+       4'b1011:	bram_reg_b <= 32'haa87ca22;
+     endcase
+
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_g_y.v b/rtl/curve/rom/brom_p384_g_y.v
index c2461eb..e64d9aa 100644
--- a/rtl/curve/rom/brom_p384_g_y.v
+++ b/rtl/curve/rom/brom_p384_g_y.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_g_y
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-
+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h90ea0e5f;
-			3'b0001:	bram_reg_b <= 32'h7a431d7c;
-			4'b0010:	bram_reg_b <= 32'h1d7e819d;
-			4'b0011:	bram_reg_b <= 32'h0a60b1ce;
-			4'b0100:	bram_reg_b <= 32'hb5f0b8c0;
-			4'b0101:	bram_reg_b <= 32'he9da3113;
-			4'b0110:	bram_reg_b <= 32'h289a147c;
-			4'b0111:	bram_reg_b <= 32'hf8f41dbd;
-			4'b1000:	bram_reg_b <= 32'h9292dc29;
-			4'b1001:	bram_reg_b <= 32'h5d9e98bf;
-			4'b1010:	bram_reg_b <= 32'h96262c6f;
-			4'b1011:	bram_reg_b <= 32'h3617de4a;
-		endcase
-		
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h90ea0e5f;
+       3'b0001:	bram_reg_b <= 32'h7a431d7c;
+       4'b0010:	bram_reg_b <= 32'h1d7e819d;
+       4'b0011:	bram_reg_b <= 32'h0a60b1ce;
+       4'b0100:	bram_reg_b <= 32'hb5f0b8c0;
+       4'b0101:	bram_reg_b <= 32'he9da3113;
+       4'b0110:	bram_reg_b <= 32'h289a147c;
+       4'b0111:	bram_reg_b <= 32'hf8f41dbd;
+       4'b1000:	bram_reg_b <= 32'h9292dc29;
+       4'b1001:	bram_reg_b <= 32'h5d9e98bf;
+       4'b1010:	bram_reg_b <= 32'h96262c6f;
+       4'b1011:	bram_reg_b <= 32'h3617de4a;
+     endcase
+
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_h_x.v b/rtl/curve/rom/brom_p384_h_x.v
index a6c474e..b6a0886 100644
--- a/rtl/curve/rom/brom_p384_h_x.v
+++ b/rtl/curve/rom/brom_p384_h_x.v
@@ -33,39 +33,39 @@
 `timescale 1ns / 1ps
 
 module brom_p384_h_x
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h1b13ea8a;
-			4'b0001:	bram_reg_b <= 32'h8b574391;
-			4'b0010:	bram_reg_b <= 32'h8155ad27;
-			4'b0011:	bram_reg_b <= 32'h55fa1b42;
-			4'b0100:	bram_reg_b <= 32'hfb57ab8d;
-			4'b0101:	bram_reg_b <= 32'h4c117c3e;
-			4'b0110:	bram_reg_b <= 32'he8b0c8cf;
-			4'b0111:	bram_reg_b <= 32'h23c5893a;
-			4'b1000:	bram_reg_b <= 32'h19bea517;
-			4'b1001:	bram_reg_b <= 32'he29c71c2;
-			4'b1010:	bram_reg_b <= 32'h82e9f590;
-			4'b1011:	bram_reg_b <= 32'haaf06bba;
-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h1b13ea8a;
+       4'b0001:	bram_reg_b <= 32'h8b574391;
+       4'b0010:	bram_reg_b <= 32'h8155ad27;
+       4'b0011:	bram_reg_b <= 32'h55fa1b42;
+       4'b0100:	bram_reg_b <= 32'hfb57ab8d;
+       4'b0101:	bram_reg_b <= 32'h4c117c3e;
+       4'b0110:	bram_reg_b <= 32'he8b0c8cf;
+       4'b0111:	bram_reg_b <= 32'h23c5893a;
+       4'b1000:	bram_reg_b <= 32'h19bea517;
+       4'b1001:	bram_reg_b <= 32'he29c71c2;
+       4'b1010:	bram_reg_b <= 32'h82e9f590;
+       4'b1011:	bram_reg_b <= 32'haaf06bba;
+     endcase
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_h_y.v b/rtl/curve/rom/brom_p384_h_y.v
index 98c59ed..c390e3d 100644
--- a/rtl/curve/rom/brom_p384_h_y.v
+++ b/rtl/curve/rom/brom_p384_h_y.v
@@ -33,39 +33,39 @@
 `timescale 1ns / 1ps
 
 module brom_p384_h_y
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-
+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h6f15f19d;
-			4'b0001:	bram_reg_b <= 32'h85bce284;
-			4'b0010:	bram_reg_b <= 32'he2817e62;
-			4'b0011:	bram_reg_b <= 32'hf59f4e30;
-			4'b0100:	bram_reg_b <= 32'h4a0f473e;
-			4'b0101:	bram_reg_b <= 32'h1625ceec;
-			4'b0110:	bram_reg_b <= 32'hd765eb83;
-			4'b0111:	bram_reg_b <= 32'h070be242;
-			4'b1000:	bram_reg_b <= 32'h6d6d23d6;
-			4'b1001:	bram_reg_b <= 32'ha2616740;
-			4'b1010:	bram_reg_b <= 32'h69d9d390;
-			4'b1011:	bram_reg_b <= 32'hc9e821b5;
-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h6f15f19d;
+       4'b0001:	bram_reg_b <= 32'h85bce284;
+       4'b0010:	bram_reg_b <= 32'he2817e62;
+       4'b0011:	bram_reg_b <= 32'hf59f4e30;
+       4'b0100:	bram_reg_b <= 32'h4a0f473e;
+       4'b0101:	bram_reg_b <= 32'h1625ceec;
+       4'b0110:	bram_reg_b <= 32'hd765eb83;
+       4'b0111:	bram_reg_b <= 32'h070be242;
+       4'b1000:	bram_reg_b <= 32'h6d6d23d6;
+       4'b1001:	bram_reg_b <= 32'ha2616740;
+       4'b1010:	bram_reg_b <= 32'h69d9d390;
+       4'b1011:	bram_reg_b <= 32'hc9e821b5;
+     endcase
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_one.v b/rtl/curve/rom/brom_p384_one.v
index fa8caa0..c8ec6c3 100644
--- a/rtl/curve/rom/brom_p384_one.v
+++ b/rtl/curve/rom/brom_p384_one.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_one
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
 
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'h00000001;
-			4'b0001:	bram_reg_b <= 32'h00000000;
-			4'b0010:	bram_reg_b <= 32'h00000000;
-			4'b0011:	bram_reg_b <= 32'h00000000;
-			4'b0100:	bram_reg_b <= 32'h00000000;
-			4'b0101:	bram_reg_b <= 32'h00000000;
-			4'b0110:	bram_reg_b <= 32'h00000000;
-			4'b0111:	bram_reg_b <= 32'h00000000;
-			4'b1000:	bram_reg_b <= 32'h00000000;
-			4'b1001:	bram_reg_b <= 32'h00000000;
-			4'b1010:	bram_reg_b <= 32'h00000000;
-			4'b1011:	bram_reg_b <= 32'h00000000;
-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'h00000001;
+       4'b0001:	bram_reg_b <= 32'h00000000;
+       4'b0010:	bram_reg_b <= 32'h00000000;
+       4'b0011:	bram_reg_b <= 32'h00000000;
+       4'b0100:	bram_reg_b <= 32'h00000000;
+       4'b0101:	bram_reg_b <= 32'h00000000;
+       4'b0110:	bram_reg_b <= 32'h00000000;
+       4'b0111:	bram_reg_b <= 32'h00000000;
+       4'b1000:	bram_reg_b <= 32'h00000000;
+       4'b1001:	bram_reg_b <= 32'h00000000;
+       4'b1010:	bram_reg_b <= 32'h00000000;
+       4'b1011:	bram_reg_b <= 32'h00000000;
+     endcase
 
 
 endmodule
diff --git a/rtl/curve/rom/brom_p384_q.v b/rtl/curve/rom/brom_p384_q.v
index 497c634..7571305 100644
--- a/rtl/curve/rom/brom_p384_q.v
+++ b/rtl/curve/rom/brom_p384_q.v
@@ -33,40 +33,40 @@
 `timescale 1ns / 1ps
 
 module brom_p384_q
-   (
-		input		wire				clk,
-		input		wire	[ 4-1:0]	b_addr,
-		output	wire	[32-1:0]	b_out
-    );
+  (
+   input wire 		clk,
+   input wire [ 4-1:0] 	b_addr,
+   output wire [32-1:0] b_out
+   );
 
 
    //
    // Output Registers
    //
-   reg [31:0] bram_reg_b;
+   reg [31:0] 		bram_reg_b;
 
    assign b_out = bram_reg_b;
-
+
 
    //
    // Read-Only Port B
-	//
-	always @(posedge clk)
-		//
-		case (b_addr)
-			4'b0000:	bram_reg_b <= 32'hffffffff;
-			4'b0001:	bram_reg_b <= 32'h00000000;
-			4'b0010:	bram_reg_b <= 32'h00000000;
-			4'b0011:	bram_reg_b <= 32'hffffffff;
-			4'b0100:	bram_reg_b <= 32'hfffffffe;
-			4'b0101:	bram_reg_b <= 32'hffffffff;
-			4'b0110:	bram_reg_b <= 32'hffffffff;
-			4'b0111:	bram_reg_b <= 32'hffffffff;
-			4'b1000:	bram_reg_b <= 32'hffffffff;
-			4'b1001:	bram_reg_b <= 32'hffffffff;
-			4'b1010:	bram_reg_b <= 32'hffffffff;
-			4'b1011:	bram_reg_b <= 32'hffffffff;
-		endcase
+   //
+   always @(posedge clk)
+     //
+     case (b_addr)
+       4'b0000:	bram_reg_b <= 32'hffffffff;
+       4'b0001:	bram_reg_b <= 32'h00000000;
+       4'b0010:	bram_reg_b <= 32'h00000000;
+       4'b0011:	bram_reg_b <= 32'hffffffff;
+       4'b0100:	bram_reg_b <= 32'hfffffffe;
+       4'b0101:	bram_reg_b <= 32'hffffffff;
+       4'b0110:	bram_reg_b <= 32'hffffffff;
+       4'b0111:	bram_reg_b <= 32'hffffffff;
+       4'b1000:	bram_reg_b <= 32'hffffffff;
+       4'b1001:	bram_reg_b <= 32'hffffffff;
+       4'b1010:	bram_reg_b <= 32'hffffffff;
+       4'b1011:	bram_reg_b <= 32'hffffffff;
+     endcase
+
 
-		
 endmodule
diff --git a/rtl/curve/rom/brom_p384_zero.v b/rtl/curve/rom/brom_p384_zero.v
index 5166391..efac8e8 100644
--- a/rtl/curve/rom/brom_p384_zero.v
+++ b/rtl/curve/rom/brom_p384_zero.v
@@ -33,10 +33,10 @@
 `timescale 1ns / 1ps
 
 module brom_p384_zero
-   (
-		output	wire	[32-1:0]	b_out
-    );
-
-	assign b_out = {32{1'b0}};
+  (
+   output wire [32-1:0] b_out
+   );
+
+   assign b_out = {32{1'b0}};
 
 endmodule
-- 
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