diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-01 23:58:31 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-01 23:58:31 +0300 |
| commit | b581d081f169bcc8afaf0072b466faf066736cee (patch) | |
| tree | b33dd94528603a083deed7130845bcbc6143e5ea /rtl | |
| parent | c09de3ee3a303bfab596def8e0b5c8b845e5a97f (diff) | |
Minor cleanup.
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/ecdsa384_wrapper.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/rtl/ecdsa384_wrapper.v b/rtl/ecdsa384_wrapper.v index 10e7c9c..672be96 100644 --- a/rtl/ecdsa384_wrapper.v +++ b/rtl/ecdsa384_wrapper.v @@ -138,8 +138,8 @@ module ecdsa384_wrapper // case (addr_lsb) // - ADDR_CONTROL: reg_control <= write_data[1]; - ADDR_DUMMY: reg_dummy <= write_data[31:0]; + ADDR_CONTROL: reg_control <= write_data[CONTROL_NEXT_BIT]; + ADDR_DUMMY: reg_dummy <= write_data; // endcase // @@ -169,7 +169,7 @@ module ecdsa384_wrapper // Register / Core Memory Selector // reg addr_msb_last; - always @(posedge clk) addr_msb_last = addr_msb; + always @(posedge clk) addr_msb_last <= addr_msb; assign read_data = (addr_msb_last == ADDR_MSB_REGS) ? tmp_read_data : read_data_core; |