diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-02 14:41:42 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2018-04-02 14:41:42 +0300 |
| commit | 0332f99f8b9ef7ec9e520406abfe887a185ec87b (patch) | |
| tree | f6a96bf6b2cb43bcde52ef60e2204285ab82f1ec /rtl | |
| parent | b581d081f169bcc8afaf0072b466faf066736cee (diff) | |
Same changes as for the P-256 core.
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/curve/rom/brom_p384_h_x.v | 25 | ||||
| -rw-r--r-- | rtl/curve/rom/brom_p384_h_y.v | 24 |
2 files changed, 25 insertions, 24 deletions
diff --git a/rtl/curve/rom/brom_p384_h_x.v b/rtl/curve/rom/brom_p384_h_x.v index b6a0886..5fef79a 100644 --- a/rtl/curve/rom/brom_p384_h_x.v +++ b/rtl/curve/rom/brom_p384_h_x.v @@ -54,18 +54,19 @@ module brom_p384_h_x always @(posedge clk) // case (b_addr) - 4'b0000: bram_reg_b <= 32'h1b13ea8a; - 4'b0001: bram_reg_b <= 32'h8b574391; - 4'b0010: bram_reg_b <= 32'h8155ad27; - 4'b0011: bram_reg_b <= 32'h55fa1b42; - 4'b0100: bram_reg_b <= 32'hfb57ab8d; - 4'b0101: bram_reg_b <= 32'h4c117c3e; - 4'b0110: bram_reg_b <= 32'he8b0c8cf; - 4'b0111: bram_reg_b <= 32'h23c5893a; - 4'b1000: bram_reg_b <= 32'h19bea517; - 4'b1001: bram_reg_b <= 32'he29c71c2; - 4'b1010: bram_reg_b <= 32'h82e9f590; - 4'b1011: bram_reg_b <= 32'haaf06bba; + 4'b0000: bram_reg_b <= 32'h5295df61; + 4'b0001: bram_reg_b <= 32'h5b96a9c7; + 4'b0010: bram_reg_b <= 32'hbe0e64f8; + 4'b0011: bram_reg_b <= 32'h4fe0e86e; + 4'b0100: bram_reg_b <= 32'h9fb96e9e; + 4'b0101: bram_reg_b <= 32'h51d207d1; + 4'b0110: bram_reg_b <= 32'ha6f434d6; + 4'b0111: bram_reg_b <= 32'h89025959; + 4'b1000: bram_reg_b <= 32'hc55b97f0; + 4'b1001: bram_reg_b <= 32'h69260045; + 4'b1010: bram_reg_b <= 32'h7ba3d2d9; + 4'b1011: bram_reg_b <= 32'h08d99905; endcase + endmodule diff --git a/rtl/curve/rom/brom_p384_h_y.v b/rtl/curve/rom/brom_p384_h_y.v index c390e3d..f56efc5 100644 --- a/rtl/curve/rom/brom_p384_h_y.v +++ b/rtl/curve/rom/brom_p384_h_y.v @@ -54,18 +54,18 @@ module brom_p384_h_y always @(posedge clk) // case (b_addr) - 4'b0000: bram_reg_b <= 32'h6f15f19d; - 4'b0001: bram_reg_b <= 32'h85bce284; - 4'b0010: bram_reg_b <= 32'he2817e62; - 4'b0011: bram_reg_b <= 32'hf59f4e30; - 4'b0100: bram_reg_b <= 32'h4a0f473e; - 4'b0101: bram_reg_b <= 32'h1625ceec; - 4'b0110: bram_reg_b <= 32'hd765eb83; - 4'b0111: bram_reg_b <= 32'h070be242; - 4'b1000: bram_reg_b <= 32'h6d6d23d6; - 4'b1001: bram_reg_b <= 32'ha2616740; - 4'b1010: bram_reg_b <= 32'h69d9d390; - 4'b1011: bram_reg_b <= 32'hc9e821b5; + 4'b0000: bram_reg_b <= 32'h0a940e80; + 4'b0001: bram_reg_b <= 32'h61501e70; + 4'b0010: bram_reg_b <= 32'h4d39e22d; + 4'b0011: bram_reg_b <= 32'h5ffd43e9; + 4'b0100: bram_reg_b <= 32'h256ab425; + 4'b0101: bram_reg_b <= 32'h904e505f; + 4'b0110: bram_reg_b <= 32'hbc6cc43e; + 4'b0111: bram_reg_b <= 32'hb275d875; + 4'b1000: bram_reg_b <= 32'hfd6dba74; + 4'b1001: bram_reg_b <= 32'hb7bfe8df; + 4'b1010: bram_reg_b <= 32'h5b1b3ced; + 4'b1011: bram_reg_b <= 32'h8e80f1fa; endcase endmodule |