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|
`timescale 1ns / 1ps
module modexps6_adder64_carry32
(
clk, t, x, y, s, c_in, c_out
);
//
// Ports
//
input wire clk;
input wire [31: 0] t;
input wire [31: 0] x;
input wire [31: 0] y;
output wire [31: 0] s;
input wire [31: 0] c_in;
output wire [31: 0] c_out;
//
// Multiplier
//
wire [63: 0] multiplier_out;
multiplier_s6 dsp_multiplier
(
.clk (clk),
.a (x),
.b (y),
.p (multiplier_out)
);
//
// Carry and T
//
wire [63: 0] t_ext = {{32{1'b0}}, t};
wire [63: 0] c_ext = {{32{1'b0}}, c_in};
//
// Sum
//
wire [63: 0] sum = multiplier_out + c_in + t;
//
// Output
//
assign s = sum[31: 0];
assign c_out = sum[63:32];
/*
reg [31: 0] s_reg;
reg [31: 0] c_out_reg;
assign s = s_reg;
assign c_out = c_out_reg;
always @(posedge clk) begin
//
s_reg <= sum[31: 0];
c_out_reg <= sum[63:32];
//
end
*/
endmodule
|
