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/*******************************************************************************
*     Generated from core with identifier: xilinx.com:ip:mult_gen:11.2         *
*                                                                              *
*     Multiplication is a fundamental DSP operation.  This core allows         *
*     parallel and constant-coefficient multipliers to be generated.  The      *
*     user can specify if dedicated hardware multipliers, slice logic or a     *
*     combination of resources should be utilized.                             *
*******************************************************************************/

// Interfaces:
//    a_intf
//    clk_intf
//    sclr_intf
//    ce_intf
//    b_intf
//    zero_detect_intf
//    p_intf
//    pcasc_intf

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
multiplier_s6 your_instance_name (
  .clk(clk), // input clk
  .a(a), // input [31 : 0] a
  .b(b), // input [31 : 0] b
  .p(p) // output [63 : 0] p
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file multiplier_s6.v when simulating
// the core, multiplier_s6. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".