Generating IP... Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten. Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. A core named 'multiplier_s6' already exists in the project. Output products for this core may be overwritten. Pre-processing HDL files for 'multiplier_s6'... Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. Finished generation of ASY schematic symbol. Finished FLIST file generation.