From 1acddf19bb8c39f5202d80af068b5ffd14797f4b Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Fri, 17 Jul 2015 11:57:51 -0400 Subject: Initial commit --- src/rtl/ipcore/subtractor_s6.xco | 73 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 src/rtl/ipcore/subtractor_s6.xco (limited to 'src/rtl/ipcore/subtractor_s6.xco') diff --git a/src/rtl/ipcore/subtractor_s6.xco b/src/rtl/ipcore/subtractor_s6.xco new file mode 100644 index 0000000..3c4f664 --- /dev/null +++ b/src/rtl/ipcore/subtractor_s6.xco @@ -0,0 +1,73 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Fri Jul 10 14:50:21 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:c_addsub:11.0 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0 +# END Select +# BEGIN Parameters +CSET a_type=Unsigned +CSET a_width=32 +CSET add_mode=Subtract +CSET ainit_value=0 +CSET b_constant=false +CSET b_type=Unsigned +CSET b_value=00000000000000000000000000000000 +CSET b_width=32 +CSET borrow_sense=Active_High +CSET bypass=false +CSET bypass_ce_priority=CE_Overrides_Bypass +CSET bypass_sense=Active_High +CSET c_in=true +CSET c_out=true +CSET ce=false +CSET component_name=subtractor_s6 +CSET implementation=DSP48 +CSET latency=0 +CSET latency_configuration=Manual +CSET out_width=32 +CSET sclr=false +CSET sinit=false +CSET sinit_value=0 +CSET sset=false +CSET sync_ce_priority=Sync_Overrides_CE +CSET sync_ctrl_priority=Reset_Overrides_Set +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-07-22T10:35:41Z +# END Extra information +GENERATE +# CRC: aaca9d7a -- cgit v1.2.3