From 1acddf19bb8c39f5202d80af068b5ffd14797f4b Mon Sep 17 00:00:00 2001 From: Paul Selkirk Date: Fri, 17 Jul 2015 11:57:51 -0400 Subject: Initial commit --- src/rtl/ipcore/multiplier_s6.xco | 68 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 src/rtl/ipcore/multiplier_s6.xco (limited to 'src/rtl/ipcore/multiplier_s6.xco') diff --git a/src/rtl/ipcore/multiplier_s6.xco b/src/rtl/ipcore/multiplier_s6.xco new file mode 100644 index 0000000..5dcc8fd --- /dev/null +++ b/src/rtl/ipcore/multiplier_s6.xco @@ -0,0 +1,68 @@ +############################################################## +# +# Xilinx Core Generator version 14.7 +# Date: Fri Jul 10 14:51:47 2015 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# Generated from component: xilinx.com:ip:mult_gen:11.2 +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = true +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc6slx45 +SET devicefamily = spartan6 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = csg324 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -3 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Multiplier xilinx.com:ip:mult_gen:11.2 +# END Select +# BEGIN Parameters +CSET ccmimp=Distributed_Memory +CSET clockenable=false +CSET component_name=multiplier_s6 +CSET constvalue=129 +CSET internaluser=0 +CSET multiplier_construction=Use_Mults +CSET multtype=Parallel_Multiplier +CSET optgoal=Speed +CSET outputwidthhigh=63 +CSET outputwidthlow=0 +CSET pipestages=2 +CSET portatype=Unsigned +CSET portawidth=32 +CSET portbtype=Unsigned +CSET portbwidth=32 +CSET roundpoint=0 +CSET sclrcepriority=SCLR_Overrides_CE +CSET syncclear=false +CSET use_custom_output_width=false +CSET userounding=false +CSET zerodetect=false +# END Parameters +# BEGIN Extra information +MISC pkg_timestamp=2013-07-22T11:36:26Z +# END Extra information +GENERATE +# CRC: 66788057 -- cgit v1.2.3