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|
module modexpng_recombinator_cell
(
clk,
ce, clr,
din, dout
);
//
// Headers
//
`include "../rtl/modexpng_parameters.vh"
//
// Ports
//
input clk;
input ce;
input clr;
input [ MAC_W -1:0] din;
output [WORD_W -1:0] dout;
reg [WORD_W -2:0] z;
reg [WORD_W :0] y;
reg [WORD_W +1:0] x;
assign dout = x[WORD_W-1:0];
wire [WORD_W -2:0] din_z = din[3*WORD_W -2 :2*WORD_W]; // [46:32]
wire [WORD_W -1:0] din_y = din[2*WORD_W -1 : WORD_W]; // [31:16]
wire [WORD_W -1:0] din_x = din[ WORD_W -1 : 0]; // [15: 0]
always @(posedge clk)
//
if (ce) begin
z <= din_z;
y <= clr ? {1'b0, din_y} : {1'b0, din_y} + {2'b00, z};
x <= clr ? {2'b00, din_x} : {2'b00, din_x} + {1'b0, y} + {WORD_ZERO, x[WORD_EXT_W-1:WORD_W]};
end
endmodule
|
