module modexpng_recombinator_block
(
    clk,
    ce, clr,
    din, dout
);

    input         clk;
    input         ce;
    input         clr;
    input  [46:0] din;
    output [15:0] dout;

    reg [14:0] z;
    reg [16:0] y;
    reg [17:0] x;
    //reg [15:0] w;

    //assign dout = w;
    assign dout = x[15:0];
    
    wire [14:0] din_z = din[46:32]; // TODO: maybe determine more precise bound here
    wire [15:0] din_y = din[31:16];
    wire [15:0] din_x = din[15: 0];
    
    always @(posedge clk)
        //
        if (ce) begin
            z <= din_z;
            y <= clr ? {1'b0, din_y}  : {1'b0, din_y} + {2'b00, z};
            x <= clr ? {2'b00, din_x} : {2'b00, din_x} + {1'b0, y} + {{16{1'b0}}, x[17:16]};
            //w <= clr ? {16{1'bX}}     : x[15:0];        
        end
    
endmodule